Title:
HardwareSolutionforRSEncodingandDecodinginWideBand
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Description: Proposed IDFT Euclidean algorithm and the combination of RS code decoding program flow, and FPGA chip to be realized. Computer simulation and measurement show that the program in the GF (28) the symbol rate up to 50MHz and above, the biggest delay for 640ns, to meet the high-speed broadband wireless access network antijamming codec needs.
To Search:
- [RSCodecSim] - err
- [Show] - Read from the file form information, and
- [c51display] - C51 a simple switch-on procedure, PELCO
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