Description: veriog realize high-speed 128-bit adder, fpga realize
- [adder16bit] - 16 high-speed adder using Verilog langua
- [trafficLight-verilog] - traffic lights to achieve the state mach
- [LAC_adder16] - 16-ahead adder, Verilog HDL
- [FAT16] - The inside has FAT16 file system source
- [IRDA] - Introduce the main infrared receiver and
- [sin] - Using the sin function delphi own discre
- [java_model] - java design patterns exercises and class
- [add] - Introduced carry_chain_adder, carry_skip
- [add_64] - Verilog 64-bit adder, and they hope to h
- [EPCS] - EPCS FPGA Quartus
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