- Category:
- SCM
- Tags:
-
[ASM]
[源码]
- File Size:
- 487.44kb
- Update:
- 2008-10-13
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- Uploaded by:
- z-ym364203
Description: CIC2 times the single-stage interpolation filter, used to achieve verilogHDL
- [CIC] - Introduced the integral comb filter (CIC
- [cic] - Verilog code written by CIC filter proce
- [DWR_cn_document] - DWR Chinese document. Including DWR entr
- [PipeCom1111] - PipeCom use named pipes to communicate.
- [CIC] - VHDL internal training materials (CIC).
- [cordic] - CIC filter source code, Verilog has writ
- [cic3s32] - Order CIC filter 32 times the extraction
- [s_filter] - FPGA realization of image filtering, rea
- [ddachabu] - NC integral to the figures, differential
- [cic_intp_64_four] - 4-order interpolating CIC filter interpo
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