uart-verilog-vhdl with vhdl and verilog prepared b - CodeBus

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Title: uart-verilog-vhdl

Category:
VHDL-FPGA-Verilog
Tags:
[Linux] [C/C++] [源码]
File Size:
288.49kb
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
刘索山

Description: with vhdl and verilog prepared by the serial communication code (synthesis)

Downloaders recently: [More information of uploader 刘索山]

To Search: uart verilog uart verilog uart vhdl Verilog UART vhdl uart VHDL uart verilog code verilog code for uart uart verilog code

[board_diag] - they simply on the development of the ni
[Uart_TR] - Verilog prepared by the simple asynchron
[UART_ise7_bak] - using FPGA full-duplex asynchronous seri
[very-good-ok-ref-ddr-sdram-verilog] - Sdr SDRAM controller reference design, v
[vga_lcd] - FPGA-based interface the lcd procedures,
[uart] - Using Verilog realization of serial asyn
[LDPC_Encoder_Verilog] - Verilog languages LDPC coding procedures
[xilinx_uart_vhdl] - This is the Xilinx
[FPGA-DDS] - In the FPGA in order to achieve the look
[singlecpu] - Analog single-clock CPU, can achieve the

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