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Description: xmlParser解析库for iphone 移植版,xcode直接可用,简单好用,大力推荐-XMLparser analytic version of the Treasury for iphone transplantation, xcode directly available, easy-to-use, highly recommended
Platform: |
Size: 594944 |
Author: minking |
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Description: 串口通信程序，包含vc界面，很好用的哦，不会还少字数吧-Serial communication program, including vc interface, good use of Oh, no less the number of words it
Platform: |
Size: 25600 |
Author: 战争oo古树 |
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Description: FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results.
here is what I do:
1- from core generator I choose fft core and create .vhd & .vho & .xco files.
2- I add the .xco & .vhd files to my project.
3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.-FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results.
here is what I do:
1- from core generator I choose fft core and create .vhd & .vho & .xco files.
2- I add the .xco & .vhd files to my project.
3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.
Platform: |
Size: 6144 |
Author: Jayesh |
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Description: 实现互相关运算 C实现，实现互相关运算 C实现-cross correlation C code implementation
Platform: |
Size: 113664 |
Author: york |
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Description: my_atan_cordic.xco - Core parameter file
my_atan_cordic.vho - Core VHDL instantiation template
my_atan_cordic.vhd - Core VHDL simulation file (only for simulation)
my_atan_cordic.edn - Core EIDF netlist (only for implementation)
x_in_cos.dat - input data for the simulation (only for simulation)
y_in_cos.dat - input data for the simulation (only for simulation)
cordic_functional.do - ModelSim do file for functional simulation
cordic_timing.do - ModelSim do file for timing simulation
design_top.ucf - contrsaints file (only for implementation)
design_top.vhd - VHDL toplevel
design_top_tb.vhd - VHDL testbench
Platform: |
Size: 118784 |
Author: d |
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Description: xcode 写的combox 控件，很方便使用，xco de 写的combox 控件，很方便使用，-it good combos
Platform: |
Size: 82944 |
Author: yyy |
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Description: Modeling of Passenger Ride-Comfort Enhancement through Designing Seat Cushion with Scilab-Xco
Platform: |
Size: 2055364 |
Author: nrmoaz |
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