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[VHDL-FPGA-VerilogPCB(Cadence)

Description: * DESCRIPTION: DDS design BY PLD DEVICES. * * AUTHOR: Sun Yu * * HISTORY: 12/06/2002 *-* DESCRIPTION : DDS BY PLD design Online.** AUTHOR : Sun Yu** HISTORY : 12/06/2002*
Platform: | Size: 467968 | Author: 魏杰 | Hits:

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