Description: wishbone总线的VHDL源代码
wishbone适用于与FPGA中IP核的高速通信，其接口简单，速度快 成为ip通信的主流-Wishbone Bus VHDL source code Wishbone applicable to IP core in FPGA high-speed communications, and its easy interface, fast becoming the mainstream of ip communications Platform: |
Size: 464896 |
Author:王鹏 |
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Description: uart16550 is a 16550 compatible (mostly) UART core.
The bus interface is WISHBONE SoC bus Rev. B.
Features all the standard options of the 16550 UART:
FIFO based operation, interrupt requests and other.
The datasheet can be downloaded from the CVS tree along with the source code. -uart16550 is a 16550 compatible (mostly) UART core.
The bus interface is WISHBONE SoC bus Rev. B.
Features all the standard options of the 16550 UART:
FIFO based operation, interrupt requests and other.
The datasheet can be downloaded from the CVS tree along with the source code.
Platform: |
Size: 1760256 |
Author:CloudZhang |
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Search - wishbone bus interface code VHDL