Description: (2,1,9)卷积编解码器，译码部分采用Vitebi译码算法，设计使用Verilog HDL语言，在Modelsim平台下仿真通过-(2,1,9) convolutional codec, decoding part decoding algorithm used Vitebi design using Verilog HDL language simulation in ModelSim platform through Platform: |
Size: 10240 |
Author:rxl |
Hits:
Description: 对于语音信号的Viterbi算法的简单仿真实现 在QuartusII下-Viterbi algorithm for speech signals simple simulation to achieve in the next QuartusII Platform: |
Size: 1024 |
Author:房先生 |
Hits:
Search - viterbi algorithm in VHDL