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[VHDL-FPGA-Verilog] FPGA_UART

Description: 异步通信串行口设计实例，很实用。比较经典。-Asynchronous serial port communications design example, it is practical. Comparison of the classic.
Platform: | Size: 493568 | Author: 王网 | Hits:

[VHDL-FPGA-Verilog] UART

Description: Hardware Design with VHDL Design Example: UART
Platform: | Size: 54272 | Author: j | Hits:

[Windows Develop] Example_UART

Description: example uart desing on VHDL.it is pro
Platform: | Size: 71680 | Author: chuyen | Hits:

[VHDL-FPGA-Verilog] uart-vhdl-testbench

Description: simple uart vhdl behavioural model (package) vhdl testbench example
Platform: | Size: 2048 | Author: Mark | Hits:

[VHDL-FPGA-Verilog] example

Description: 我FPGA开发板的程序！！！包括数、码管iic、VGA、乘法器、串口。加法器、比较器、状态机等等等了，主要是VHDL的也有部分好似Verilog的。参考下吧-verilog...vga..uart...add...etc..
Platform: | Size: 6266880 | Author: 地主 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 一个功能很强大的异步串口例子，用vhdl完成，波特率等参数可以调整。-A feature very powerful example of asynchronous serial interface, complete with vhdl, baud rate parameters can be adjusted.
Platform: | Size: 4096 | Author: tofly | Hits:

[Software Engineering] aima

Description: 基于DMA通过UART发送和接收数据的例子，注意DMA_0为接受通道，DMA_1为发送通道。当然可以将dma的read_master和writer_master同时连在uart_0和sdram_0的从端口上，这样是可以用一个dma对两者读写操作，但是不能同时做双向传输。-Based on DMA send and receive data through the UART example, attention DMA_0 accepted channels, DMA_1 to send the channel. Can, of course dma' s read_master and writer_master the same time even in the uart_0 and sdram_0 from the port, it can both read and write on using a dma operation, but can not simultaneously do two-way transmission.
Platform: | Size: 1024 | Author: 王星龙 | Hits:

[Com Port] RS232

Description: simple example for uart on fpga
Platform: | Size: 714752 | Author: Jay | Hits:

[VHDL-FPGA-Verilog] UART_EX

Description: Uart 232 module example divied by 3 module.
Platform: | Size: 4096 | Author: park wan soon | Hits:

[VHDL-FPGA-Verilog] Uart._VHDL

Description: 很不错的串口程序，用VHDL语言写的，大家可以参考下。-it s a very good example for fpga applying on the uart communition,which is compiled by VHDL
Platform: | Size: 631808 | Author: 杜峰 | Hits:

[VHDL-FPGA-Verilog] RS232-Simple

Description: A simple UART example for reference in VHDL.
Platform: | Size: 71680 | Author: Cong | Hits:

[VHDL-FPGA-Verilog] UART-VHDL-Example-Code-for-an-FPGA-or-ASIC-from-n

Description: UART code using VHDL for FPGA or ASIC
Platform: | Size: 10240 | Author: dani | Hits:

[VHDL-FPGA-Verilog] URAT

Description: 在ISE环境下，用VHDL语言实现RS232串口设计，实现串口通信。通过串口调试工具向 0000000UART发送16进制数，FPGA将UART接收到的串行数据转换为并行数据，并在8个 LED灯上输出显示；同时，并行数据又被重新转换为串行数据，重新送给RS-232接口，并在 串口调试工具上再次显示，SW0为复位键。 比如：串口调试工具发送两位16进制数，然后能在LED上显示，并且重新在串口调试工 具上显示。串口调试工具设置：波特率设为9600，默认奇校验。-In the ISE environment, using VHDL language RS232 serial port design, serial communication. Through the serial debugging tool to 0000000UART Send a hexadecimal number, FPGA serial data received by the UART converted to parallel data, and 8 LED lights on the output display the same time, parallel data has been re-converted to serial data, re-sent to the RS-232 interface, and in Serial debugging tools on the show again, SW0 for the reset button. For example: serial debugging tool to send two 16 hexadecimal number, and then can be displayed on the LED, and re-debugging in the serial port With a display. Serial debugging tool settings: baud rate is set to 9600, the default odd parity.
Platform: | Size: 403456 | Author: panda | Hits:

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