Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - vhdl testben

Search list

[Books] VHDL_TESTBENCH

Description: 怎样用VHDL写TESTBENCH.rar VHDL仿真-how to use VHDL to write VHDL simulation TESTBENCH.rar
Platform: | Size: 9594880 | Author: 高 | Hits:

[Other] Testbench

Description: 单顶层结构化Testbench设计实例，适合硬件开发人员作为参考-Testbench structure of a single top-level design, suitable for hardware developers as a reference
Platform: | Size: 154624 | Author: xyq | Hits:

[source in ebook] XiaYuWen_8_RISC_CPU

Description: 夏宇闻8位RISC_CPU的完整代码+TESTBENCH（已调试） modelsim工程文件，包括书中所测试的三个程序和相关数据，绝对可用~所有信号名均遵从原书。在论坛中没有找到testbench的，只有一个mcu的代码，但很多和书中的是不一样的，自己改了下下~`````大家多多支持啊~`我觉得书中也还是有些不尽如人意的地方，如clk_gen.v中clk2,clk4是没有用的，assign clk1=~clk再用clk1的negedge clk1来触发各个module也是不太好的，会使时序恶化，综合时很可能会setup vio的，所以觉得直接用clk的上升沿来触发各个module比较好-XIA Yu-Wen 8 RISC_CPU complete code+ TESTBENCH (has debug) modelsim project documents, including the book by the three test procedures and related data, the absolute available ~ all signals were found in compliance with the original name. Not found in the forums Testbench, and there is only one mcu code, but many and the book is not the same as he changed a lot of support under the U.S. ~````` ah ~ `I think the book is still some uncertainty unsatisfactory places, such as clk_gen.v in clk2, clk4 is of no use, assign clk1 = ~ clk reuse CLK1 of negedge clk1 to trigger module is not all good, cause the deterioration of timing, synthesis is likely to setup vio, therefore, feel that the direct use of the rising edge of clk to trigger each module is better
Platform: | Size: 86016 | Author: 刘志伟 | Hits:

[VHDL-FPGA-Verilog] TestBench

Description: 怎样写testbench 本文的实际编程环境：ISE 6.2i.03 ModelSim 5.8 SE Synplify Pro 7.6 编程语言 VHDL 在ISE 中调用ModelSim 进行仿真-、assert (s_cyi((DWIDTH-1)/4) = 0 ) and (s_ovi = 0 ) and (s_qutnt = conv_std_logic_vector(v_quot,DWIDTH)) and (s_rmndr = conv_std_logic_vector(v_remd,DWIDTH)) report "ERROR in division!" severity failure
Platform: | Size: 90112 | Author: lei | Hits:

[VHDL-FPGA-Verilog] uart-vhdl-testbench

Description: simple uart vhdl behavioural model (package) vhdl testbench example
Platform: | Size: 2048 | Author: Mark | Hits:

[VHDL-FPGA-Verilog] new_fifo

Description: 最新的testbench of FIFO ，使用Vmm，VCS，可以大致了解一下VMM的体系-the new fifo VMM testbench
Platform: | Size: 6144 | Author: niusl | Hits:

[VHDL-FPGA-Verilog] Text-IO

Description: 基于VHDL的Testbench读取文件的编写，很有用的 基于VHDL的Testbench读取文件的编写，很有用的-VHDL Code text_io for the "Simple Test Bench" example VHDL Code about text_io for the "Simple Test Bench" example
Platform: | Size: 1024 | Author: 帅哥新 | Hits:

[VHDL-FPGA-Verilog] VHDL--TESTBENCH

Description: VHDL描述的TESTBENCH写法 ,对新人有帮助。-The use of VHDL to write TESTBENCH files.useful for new people
Platform: | Size: 9600000 | Author: 姜珊 | Hits:

CodeBus www.codebus.net