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[Other resourceceshixiangliang

Description: vhdl 测试向量含测试向量(Test Bench)和波形产生:VHDL实例---相应加法器的测试向量(test bench).txt-VHDL test vector containing test vector (Test Bench) and Waveform Generator : VHDL examples --- corresponding Adder test vector (test bench). Txt
Platform: | Size: 11173 | Author: 陈丽 | Hits:

[VHDL-FPGA-Verilogceshixiangliang

Description: vhdl 测试向量含测试向量(Test Bench)和波形产生:VHDL实例---相应加法器的测试向量(test bench).txt-VHDL test vector containing test vector (Test Bench) and Waveform Generator : VHDL examples--- corresponding Adder test vector (test bench). Txt
Platform: | Size: 11264 | Author: 陈丽 | Hits:

[VHDL-FPGA-Verilogfft_gen

Description: FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results. here is what I do: 1- from core generator I choose fft core and create .vhd & .vho & .xco files. 2- I add the .xco & .vhd files to my project. 3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.-FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results. here is what I do: 1- from core generator I choose fft core and create .vhd & .vho & .xco files. 2- I add the .xco & .vhd files to my project. 3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.
Platform: | Size: 6144 | Author: Jayesh | Hits:

[VHDL-FPGA-Verilogvhdl-code-for-sine-wave-generator

Description: it is a simple code in vhdl for sine wave generator. the test bench code is also provided in ths code
Platform: | Size: 21504 | Author: nasimus | Hits:

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