Search - vhdl sine generator

[VHDL-FPGA-Verilog] 一个波形发生器和sine波形发生器

Description: 这是一个典型的正玄波发生器程序和一个任意波形发生器程序，大家可以参考学习，对于vhdl入门还是很有帮助的-This is a typical wave generator Shogen procedures and an arbitrary waveform generator procedures, Members can take a learning portal for VHDL or helpful
Platform: | Size: 3072 | Author: 张云鹏 | Hits:

[assembly language] sine

Description: 用verilog语言编的正弦波发生器，可以用QuartusII来打开这个源码，也可以转换成VHDL语言-Verilog language prepared by the sine wave generator can be used QuartusII to open the source code can also be converted into VHDL language
Platform: | Size: 104448 | Author: 雨孩 | Hits:

[Documents] singt_vhdl_quartus

Description: 正弦波发生器，可以应用，开发环境QUARTUS,实验箱为GW48-Sine wave generator, can be applied, development environment QUARTUS, experimental box for GW48
Platform: | Size: 891904 | Author: 在路上 | Hits:

[VHDL-FPGA-Verilog] sin_generator

Description: 在quartus 11 5.1 里用VHDL编写的正弦波发生器，经过仿真通过-Quartus 11 5.1 years in VHDL prepared using sine wave generator, through simulation through
Platform: | Size: 245760 | Author: 郭翠双 | Hits:

[SCM] wave-generator

Description: 产生方波，三角波，正弦波，余弦波等波形，并且可以自由选择和切换，最后可以用于波形输出-Have a square wave, triangle wave, sine wave, cosine wave, such as waveform, and can freely choose and switch, and finally can be used for waveform output
Platform: | Size: 6144 | Author: 周易 | Hits:

[VHDL-FPGA-Verilog] sin

Description: 基于Quartus II 5.0编写的正弦波发生器，可控频率，用vhdl编写的-Quartus II 5.0 on the preparation of the sine wave generator, controllable frequency, prepared using VHDL
Platform: | Size: 475136 | Author: uuk | Hits:

[VHDL-FPGA-Verilog] sin

Description: 基于fpga的正弦波发生器设计，有一定的参考价值，写的比较详细-The sine wave generator based on FPGA design, have a certain reference value, a more detailed written
Platform: | Size: 632832 | Author: qlg | Hits:

[VHDL-FPGA-Verilog] sine-generator

Description: 原创：采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm生成，可产生正弦波。更改rom内容可改变波形-Original: Using VHDL languages sinusoidal signal generator. rom using Quartus LPM s own generation, can produce sine wave. Rom content changes can change the waveform
Platform: | Size: 675840 | Author: zzwuyu | Hits:

[VHDL-FPGA-Verilog] sin125

Description: 用FPGA实现DDS的信号发生器（正弦波125kHz）-Using FPGA to achieve DDS signal generator (sine wave 125kHz)
Platform: | Size: 196608 | Author: 杜海明 | Hits:

[VHDL-FPGA-Verilog] VHDL-ROM4

Description: 基于ROM的正弦波发生器的设计：1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based design of the sine wave generator: 1. Sinusoidal waveform generator by the data storage module (ROM), waveform generator control module and latch module 2. Waveform data storage module (ROM) custom data width of 8 , address width of 6, can store 64 points sinusoidal waveform data, waveform data are obtained using MATLAB. 3. To 50MHz clock as input.
Platform: | Size: 98304 | Author: 宫逢源 | Hits:

[Other] bxfsq

Description: 波形发生器的代码，具有产生正弦波、方波、三角波的功能。-Waveform Generator code has generated sine wave, square, triangle-wave function.
Platform: | Size: 16384 | Author: 李仁刚 | Hits:

[VHDL-FPGA-Verilog] signal_generator

Description: 基于vhdl的多功能函数信号发生器的设计，能实现三角波、方波、正弦波。-VHDL-based multi-function signal generator design, can achieve the triangular wave, square wave, sine wave.
Platform: | Size: 1024 | Author: tony | Hits:

[VHDL-FPGA-Verilog] sine_testbench

Description: Sine generator in VHDL.
Platform: | Size: 5120 | Author: Mike | Hits:

[Other] Sine

Description: 正弦波发生器，可以让大家学习正弦多种产生方法，可以设计具体电路-Sine wave generator, allowing them to learn the method for multiple sinusoidal, can design a specific circuit
Platform: | Size: 1028096 | Author: 秦寅 | Hits:

[VHDL-FPGA-Verilog] sWave

Description: 正弦波，Verilog波形发生器，很好的东西-Sine wave, Verilog waveform generator, a good thing
Platform: | Size: 1391616 | Author: yanppf | Hits:

[VHDL-FPGA-Verilog] sine

Description: Verlog语言描述的正弦信号发生器的源代码可以方便的实现长生正弦信号-Language Verlog sinusoidal signal generator described in the source code can easily achieve the longevity of the sinusoidal signal
Platform: | Size: 97280 | Author: wuli | Hits:

[SCM] Sine

Description: 标准正弦信号发生器,并且含有正弦表,对于新手有些帮助-Standard sinusoidal signal generator, and contain sinusoidal form, and some help for novice
Platform: | Size: 2530304 | Author: 张金斗 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 利用VHDL实现任意函数发生器，包括方波、正弦波、三角波等。-The use of VHDL to achieve arbitrary function generator, including square, sine wave, triangle wave and so on.
Platform: | Size: 39936 | Author: 陈海巍 | Hits:

[VHDL-FPGA-Verilog] VHDL(sin)

Description: 基于ROM的正弦波发生器的设计一．实验目的 1. 学习VHDL的综合设计应用 2. 学习基于ROM的正弦波发生器的设计二．实验内容设计基于ROM的正弦波发生器，对其编译，仿真。具体要求： 1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based sine wave generator design 1. Purpose of the experiment 1. VHDL Integrated Design and Application of Learning 2. Learning ROM-based sine wave generator design 2. Experimental content ROM-based sine wave generator design, its compilation, simulation. Specific requirements: 1. Sine wave generator by the data storage module (ROM), waveform generator control module and latch modules Two. Waveform data storage module (ROM) custom data width is 8, the address width of 6, can store 64-point sine wave data, wave data obtained using MATLAB. 3. The 50MHz input clock.
Platform: | Size: 17408 | Author: 爱好 | Hits:

[VHDL-FPGA-Verilog] sine-generator

Description: ROM型正弦信号发生器，从rom中读取正弦波的点，循环输出，经AD生成波形，环境为quartus-sine generator in quartus
Platform: | Size: 677888 | Author: 张文 | Hits:

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[VHDL-FPGA-Verilog] 一个波形发生器和sine波形发生器

[assembly language] sine

[Documents] singt_vhdl_quartus

[VHDL-FPGA-Verilog] sin_generator

[SCM] wave-generator

[VHDL-FPGA-Verilog] sin

[VHDL-FPGA-Verilog] sin

[VHDL-FPGA-Verilog] sine-generator

[VHDL-FPGA-Verilog] sin125

[VHDL-FPGA-Verilog] VHDL-ROM4

[Other] bxfsq

[VHDL-FPGA-Verilog] signal_generator

[VHDL-FPGA-Verilog] sine_testbench

[Other] Sine

[VHDL-FPGA-Verilog] sWave

[VHDL-FPGA-Verilog] sine

[SCM] Sine

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] VHDL(sin)

[VHDL-FPGA-Verilog] sine-generator

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