Search - vhdl sign

[AI-NN-PR] chap7

Description: 实现血红细胞的阈值变换，边缘检测，边缘提取功能 -Red blood cells to achieve the threshold transform, edge detection, edge detection function
Platform: | Size: 129024 | Author: 李蕊玲 | Hits:

[VHDL-FPGA-Verilog] accumulator

Description: 实现累加器的verilog源码，广泛应用在通信电路设计中-The realization of accumulator Verilog source, widely used in communication circuit design
Platform: | Size: 1024 | Author: 文明 | Hits:

[VHDL-FPGA-Verilog] Multi11Mulply

Description: 本程序是11位带符号位的乘法器，其中最高位为符号位(sign)，中间7位是指数部分(Exponent)，最后3位是尾数(Matissa)。表示数据的范围是-2^-63-----+2^64.该工程文件有完整的程序，以及波形,验证正确。-This procedure is the unsigned 11-bit multiplier, one of the highest for the sign bit (sign), are between 7 part Index (Exponent), the final three are mantissa (Matissa). Express the scope of the data are-2 ^-63-----+ 2 ^ 64. The project document has a complete procedures, as well as waveform, verify that the correct.
Platform: | Size: 445440 | Author: 至诚 | Hits:

[VHDL-FPGA-Verilog] 4multiplier

Description: 4位乘法器vhdl程序-- DESCRIPTION : Signed mulitplier:-- A (A) input width : 4-- B (B) input width : 4-- Q (data_out) output width : 7-4 multiplier vhdl procedure
Platform: | Size: 3072 | Author: lsp | Hits:

[VHDL-FPGA-Verilog] lunwen

Description: 潘明海　刘英哲　于维双 (论文) 中文摘要：本文讨论了一种可在FPGA上实现的FFT结构。该结构采用基于流水线结构和快速并行乘法器的蝶形处理器。乘法器采用改进的Booth算法，简化了部分积符号扩展，使用Wallace树结构和4-2压缩器对部分积归约。以8点复点FFT为实例设计相应的控制电路。使用VHDL语言完成设计，并综合到FPGA中。从综合的结果看该结构可在XC4025E-2上以52MHz的时钟高速运行。在此基础上易于扩展为大点数FFT运算结构。 -Pan Minghai Liuying Zhe Yu-dimensional pairs (thesis) Chinese Abstract: This paper discusses an FPGA can be implemented on the structure of the FFT. The architecture based on pipeline architecture and fast parallel multiplier butterfly processor. Multiplier using modified Booth algorithm simplifying the partial product sign extension, use the Wallace tree and 4-2 compressor for partial product reduction. 8-point complex-point FFT as an example design of the corresponding control circuit. To complete the design using the VHDL language, and integrated into the FPGA. From the results of a comprehensive look at the structure can be XC4025E-2 with 52MHz clock on the high-speed operation. On this basis, easy to expand the structure for large point FFT operations.
Platform: | Size: 128000 | Author: culun | Hits:

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[AI-NN-PR] chap7

[VHDL-FPGA-Verilog] accumulator

[VHDL-FPGA-Verilog] Multi11Mulply

[VHDL-FPGA-Verilog] 4multiplier

[VHDL-FPGA-Verilog] lunwen

[VHDL-FPGA-Verilog] Flag-of-asynchronous-FIFO

[VHDL-FPGA-Verilog] 1bitAdder

[source in ebook] VHDL

[VHDL-FPGA-Verilog] sign-magnitude-adder

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