Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - vhdl fpga RS232

Search list

[VHDL-FPGA-Verilog] serial_ppga

Description: 异步串口通信口在FPGA实现，功能有（1）串行数据接收的同步控制；（2） 串行数据发送的同步控制-asynchronous serial communication port of the FPGA, function (1) serial data receiver synchronization control; (2) the transmission of serial data synchronization control
Platform: | Size: 199680 | Author: 孙洪亮 | Hits:

[Post-TeleCom sofeware systems] rs232_send

Description: rs232 vhdl程序 可以实行异步串行通信,这里只有send-rs232 vhdl procedures implemented asynchronous serial communication, here only send
Platform: | Size: 1024 | Author: 李湘宏 | Hits:

[VHDL-FPGA-Verilog] vhdl_rs232

Description: 使用FPGA透过RS232与PC的作沟通，
Platform: | Size: 3072 | Author: 苏山河 | Hits:

[VHDL-FPGA-Verilog] rs232

Description: RS232 verilog design
Platform: | Size: 114688 | Author: liuKe | Hits:

[VHDL-FPGA-Verilog] cyclic

Description: FPGA的串口通信程序，可接受或者发送数据，通过Rs232口-FPGA serial communication program, acceptable, or send data through the RS232 port
Platform: | Size: 1307648 | Author: xianchunwwang | Hits:

[VHDL-FPGA-Verilog] FPGArealizeRS232

Description: 用FPGA实现RS232通信,此代码是用VHDL语言编写，非常有用的好东东啊-RS232 Communication with FPGA realize that this code is written in VHDL, very useful, good东东啊
Platform: | Size: 48128 | Author: 孙建军 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 用FPGA实现了RS232异步串行通信，所用语言是VHDL，另外本人还有Verilog的欢迎交流学习，根据RS232 异步串行通信来的帧格式，在FPGA发送模块中采用的每一帧格式为：1位开始位+8位数据位+1位奇校验位+1位停止位，波特率为2400。由设置的波特率可以算出分频系数，具体算法为分频系数X=CLK/(BOUND*2)。-Using FPGA to achieve the RS232 asynchronous serial communication, the language used is VHDL, In addition, I also welcome the exchange of learning Verilog, according to RS232 asynchronous serial communication to the frame format, in the FPGA module used to send each frame format : the beginning of a bit+ 8-bit data bit+ 1 bit odd parity bit+ 1 bit stop bit, baud rate for 2400. By setting the baud rate can be calculated at the frequency coefficient, the specific algorithm for the sub-frequency coefficient X = CLK/(BOUND* 2).
Platform: | Size: 1024 | Author: saibei007 | Hits:

[Books] ComunicationRealizationBetweenFPGAandSerialInterfa

Description: 杜晓斌和陈兴文-FPGA和单片机串行通信接口的实现一文提出了FPGA与单片机实现数据串行通信的解决方案。在通信过程中完全遵守RS232 协议，给出了发送模块的vhdl源代码。 -杜晓斌and陈兴文-FPGA single-chip serial communication interface and the realization of a text proposed by the FPGA and MCU serial data communications solutions. In the communication process in full compliance with the RS232 protocol is given to send the VHDL source code modules.
Platform: | Size: 92160 | Author: Wuxinmin | Hits:

[VHDL-FPGA-Verilog] RS232

Description: RS232串口通信协议，verilog实现，通过FPGA完全调通。-RS232 serial communication protocol, verilog achieved entirely through the FPGA transfer pass.
Platform: | Size: 3072 | Author: dingsheng | Hits:

[VHDL-FPGA-Verilog] RS232_pro

Description: RS232 verilog coding 全参数化设计 可以自己设定波特率 时钟频率等 完全FPGA实现调通-RS232 verilog coding the entire parametric design can set the baud rate clock frequency of FPGA to achieve complete transfer pass
Platform: | Size: 2048 | Author: dinsh | Hits:

[VHDL-FPGA-Verilog] Rs232sourcecode

Description: Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd - to display at 7 sgement display - D4to7 .vhd - Convert HEX decimal to ASCII code. -Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd- to display at 7 sgement display - D4to7 .vhd- Convert HEX decimal to ASCII code.
Platform: | Size: 5120 | Author: Ikki | Hits:

[Com Port] FPGArs232

Description: FPGA中实现rs232串口通信程序，上位机和FPGA互发数据-FPGA to achieve rs232 serial communication procedures, each host computer and FPGA-fat data
Platform: | Size: 100352 | Author: wg | Hits:

[VHDL-FPGA-Verilog] rs232

Description: fpga的串口读写程序，经硬件测试成功，波特率9600.可以改变分频值适应不同的时钟和波特率-fpga serial read and write procedures, by the hardware to test the success of 9600 baud rate. frequency value can be changed to adapt to a different clock and baud rate
Platform: | Size: 384000 | Author: cjy | Hits:

[VHDL-FPGA-Verilog] RS232

Description: RS232的FPGA通讯程序，用的是VHDL语言写的，非常好用-RS232 communication program of the FPGA, using the VHDL language, very easy to use
Platform: | Size: 365568 | Author: 无名氏 | Hits:

[Embeded-SCM Develop] altera-schemic-

Description: FPGA应用，Altera的FPGA开发板原理图汇集，FPGA最小系统，rs232串口转换，VGA显示-FPGA applications, Altera' s FPGA development board schematic pooling, FPGA minimum system, rs232 serial converter, VGA display etc.
Platform: | Size: 1720320 | Author: 吴贵锋 | Hits:

[Embeded-SCM Develop] c_FPGA

Description: RS232设计，硬件测试通过，VERILOG实现的，比较好的哦-RS232 design, hardware test, VERILOG realized, oh good
Platform: | Size: 1249280 | Author: 洪依 | Hits:

[VHDL-FPGA-Verilog] rs232

Description: 完整的RS232 Verilog源代码，支持波特率可调，支持调试命令，配合串口调试工具，可作为FPGA开发中的调试平台。-Full RS232 Verilog source code, support for baud rate is adjustable to support debugging command, with the serial debugging tools can be used as the debugging FPGA development platform.
Platform: | Size: 13312 | Author: 弘历 | Hits:

[VHDL-FPGA-Verilog] rs232

Description: 用vhdl实现fpga串口通信 包含 波特率生成 发送模块 接收模块 过采样 signaltap使用-Vhdl fpga serial communication with the realization of sending module contains the baud rate generation receiver module using oversampling signaltap
Platform: | Size: 2275328 | Author: adam | Hits:

[VHDL-FPGA-Verilog] RS232

Description: RS232 串口通信 的 VHDL描述，初学FPGA的朋友可以-RS232 serial communication VHDL description, FPGA beginner friends can see
Platform: | Size: 1346560 | Author: chengwenfan | Hits:

[VHDL-FPGA-Verilog] FPGA-UART

Description: 该资料是实现VHDL的串口通信(UART)，RS232接口协议，-VHDL implementation of serial communication
Platform: | Size: 2087936 | Author: lp | Hits:
« 12 3 »

CodeBus www.codebus.net