Description: 收集了很多好的风格及代码的指导准则供参考，遵守这些代码风格及代码指导准则可以提高VHDL程序的可读性，且易于修改。-collected a lot of good style and code guidelines for reference, compliance with these codes and code style guidelines VHDL procedures can improve the readability and easy to change. Platform: |
Size: 39936 |
Author:zcx |
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Description: synopsis的有限状态机编码方法的文档。
针对synopsis的综合环境，根据其综合工具的特点说明安全可靠、速度适合的FSM编码风格。
FSM coding style under synopsis. Used for verilog or vhdl designer. Good study data for ASIC newhand.-synopsis of the finite state machine coding documents. Synopsis for the integrated environment, in accordance with its characteristics of integrated tools that secure and reliable, speed appropriate FSM coding style. FSM coding style under synopsis. Used for verilog or vhdl designer. Good study data for ASIC newhand. Platform: |
Size: 119808 |
Author:road |
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Description: Altera公司高端FPGA高级综合指导手册，包括：算术运算单元，浮点处理技巧，数据编码格式转换，视频处理，仲裁逻辑，多路选择，存储逻辑，计数器，通信逻辑，循环冗余校验，随机和伪随机函数，加密和同步等编码风格和技巧；-advanced synthesis cookbook for Altera high-end FPGA(Stratix),incuding coding style and design tricks for
arithmetic,floating points operation,tranlation and format convertion,vidio, arbitor, multiplexing, registers and
memories,communication,CRC,random and pseudorandom functions,cryptography,synchronization,etc. Platform: |
Size: 962560 |
Author:刘易 |
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Description: VHDL代码编写规范与风格，XILINX培训用教材，WORD文档的，写得特好，只不过是E文的-VHDL coding and style norms, XILINX training materials, WORD documents, and written special good, but is E-man Platform: |
Size: 154624 |
Author:邓子龙 |
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Description: Several unique features distinguish the book:
* Coding style that shows a clear relationship between VHDL constructs and hardware components
* Conceptual diagrams that illustrate the realization of VHDL codes
* Emphasis on the code reuse
* Practical examples that demonstrate and reinforce design concepts, procedures, and techniques
* Two chapters on realizing sequential algorithms in hardware
* Two chapters on scalable and parameterized designs and coding
* One chapter covering the synchronization and interface between multiple clock domains
-Several unique features distinguish the book:
* Coding style that shows a clear relationship between VHDL constructs and hardware components
* Conceptual diagrams that illustrate the realization of VHDL codes
* Emphasis on the code reuse
* Practical examples that demonstrate and reinforce design concepts, procedures, and techniques
* Two chapters on realizing sequential algorithms in hardware
* Two chapters on scalable and parameterized designs and coding
* One chapter covering the synchronization and interface between multiple clock domains
Platform: |
Size: 28478464 |
Author:chane |
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Description: 讲述了HDL编码风格的一本好书，不论使用VHDL或verilog的都可以-HDL coding style tells a good book, regardless of the use of VHDL or verilog can take a look at the Platform: |
Size: 211968 |
Author:aegis |
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Description: 一个很好的关于verilog的PPT
第1章 EDA设计与Verilog HDL语言概述
第2章 Verilog HDL基础与开发平台操作指南
第3章 Verilog HDL程序结构
第4章 VERILOG HDL语言基本要素
第5章 面向综合的行为描述语句
第6章 面向验证和仿真的行为描述语句
第7章 系统任务和编译预处理语句
第8章 VERILOG HDL可综合设计的难点解析
第9章 高级逻辑设计思想与代码风格
第10章 可综合状态机开发实例
第11章 常用逻辑的VERILOG HDL实现
第12章 XILINX硬核模块的VERILOG HDL调用
第13章 串口接口的VERILOG HDL设计-A good verilog of PPT on Chapter 1 of EDA Design and Verilog HDL language outlined in Chapter 2 based on Verilog HDL and development platform Operations Guide Chapter 3 Verilog HDL program structure VERILOG HDL languages Chapter 4 Chapter 5 for the basic elements of an integrated behavioral description statement in Chapter 6 for the verification and simulation of the behavior of the system described in Chapter 7 mission statements and prepared statements compiled in Chapter 8 VERILOG HDL design can be integrated Difficulties in Chapter 9, advanced logic design and coding style Chapter 10 Comprehensive state machine instance can be developed in Chapter 11 to achieve common logic VERILOG HDL Chapter 12 XILINX hard core module VERILOG HDL called Chapter 13 Serial Interface VERILOG HDL design Platform: |
Size: 27825152 |
Author:lyy |
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Description: Verilog可综合代码编写风格介绍。属于HW中央逻辑开发部的绝密资料，加上本人的总结而成。喷血推荐。-The coding style of Verilog language. It is very useful for verilog system developer Platform: |
Size: 448512 |
Author:liangyao |
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Description: D-type storage elements
The circuit below contains three different types of storage element: a gated (transparent) D latch, a positive-edge triggered and negative edge triggered D-type flip-flops.
Write a VHDL file that instantiates the three storage elements. You can use the code for the gated D-type below as an example to get started. Use a similar coding style for the other flip-flops.
Compile your code and use the Technology Viewer to examine the implemented circuit and to determine how the synthesis process has allocated your circuit to the internal resources in the FPGA.
Using the waveform below as a guide, create a Vector Waveform File (.vwf) that specifies the inputs and expected outputs of the circuit. Perform a functional simulation to obtain the three output signals. Observe the different behaviour of the three storage elements.-D-type storage elements
The circuit below contains three different types of storage element: a gated (transparent) D latch, a positive-edge triggered and negative edge triggered D-type flip-flops.
Write a VHDL file that instantiates the three storage elements. You can use the code for the gated D-type below as an example to get started. Use a similar coding style for the other flip-flops.
Compile your code and use the Technology Viewer to examine the implemented circuit and to determine how the synthesis process has allocated your circuit to the internal resources in the FPGA.
Using the waveform below as a guide, create a Vector Waveform File (.vwf) that specifies the inputs and expected outputs of the circuit. Perform a functional simulation to obtain the three output signals. Observe the different behaviour of the three storage elements.
Platform: |
Size: 3438592 |
Author:sunyan |
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Description: 该资料对数字设计的编码风格、编码规范给出了详细介绍，并简介了VHDL、verilog的编码要点。-The information on the coding style of digital design, coding specification gives a detailed description and profile of VHDL, verilog coding points. Platform: |
Size: 63488 |
Author:zxc |
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Description: 关于状态机的规范编码风格，有具体的verilog，vhdl实例-On the norms of the state machine coding style, specific Verilog, VHDL instance Platform: |
Size: 83968 |
Author:charley |
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Description: Eda主要介绍的逻辑设计与集成电路：FPGA 设计的指导性原则（连载之二）
典型的FPGA 设计流程
大型复杂FPGA 设计推荐设计方式──Modular Design
Coding Style 与综合前后仿真
数据接口设计
关于有限状态机编码的技巧和注意事项
做distributed ram 时遇到的几个不太明白的信号
Source Insight 兼容VHDL 与VERILOG
如何实现信号延时？
[转载]新手学习技巧-EDA introduces the logical design of integrated circuits: FPGA design of the guiding principles (Part II)
Typical FPGA design flow
Large, complex FPGA design recommended design approach ─ ─ Modular Design
Coding Style and comprehensive before and after simulation
Data interface design
Finite state machine coding techniques and precautions
Do the Distributed RAM encountered a few do not quite understand the signal
Source Insight is compatible with VHDL and Verilog
How to achieve signal delay?
[Reserved] novice learning skills Platform: |
Size: 491520 |
Author:江风 |
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Search - vhdl coding style