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[Other] 74_alarm_clock111

Description: 闹钟系统，用VHDL语言进行编码， 请多指教，可能不是很好-alarm system, using VHDL coding, please enlighten, may not be very good
Platform: | Size: 3072 | Author: jinlong | Hits:

[Other] 15_MUX41

Description: 乘法器，用VHDL语言编码，可能对你用处不是很大，但做为参考还是很大用处的-multiplier using VHDL coding, you may not have much use, but as a reference or very useful
Platform: | Size: 6144 | Author: jinlong | Hits:

[Other] 53_counter11

Description: 计数器，用VHDL语言编码，可能对你用处不是很大，但做为参考还是很大用处的-counter, using VHDL coding, you may not have much use, but as a reference or very useful
Platform: | Size: 1024 | Author: jinlong | Hits:

[Software Engineering] State-Machi-ne-Coding-Styles-for-Synthesis

Description: 国外论文，超经典的状态机描述，学习vhdl必看-International Paper, ultra classic state machine description, learning VHDL must-see
Platform: | Size: 123904 | Author: 行卡 | Hits:

[Windows Develop] MC-ACT-RSENC_DS

Description: MemecCoreReed-Solomon coding is a method of forward error correction in the form of block coding. Block coding consists of calculating a number of parity symbols over a number of message symbols. The parity symbols are appended to the end of the message symbols forming a codeword. Reed-Solomon coding is described in the form RS(n,k), where k is the number of message symbols in each block and n is the total number of symbols in the codeword. The value t defines the number of symbols that can be corrected by the Reed-Solomon code, where t=(n-k)/2 and the number of parity symbols is equal to 2t.
Platform: | Size: 95232 | Author: 张波 | Hits:

[VHDL-FPGA-Verilog] LC3-VHDL-another

Description: 另一套LC3 CPU VHDL源码及设计文档，对LC3进行了一些取舍和改造，比如NZP改为NZC，更贴近现实CPU硬件架构。按照ASM进行VHDL编码，更适合数字设计初学者学习。-Another set of LC3 CPU VHDL source code and design documents, of LC3 to a number of trade-offs and transformation, such as NZP changed NZC, more close to reality CPU hardware architecture. In accordance with the ASM to VHDL coding, digital design more suitable for beginners to learn.
Platform: | Size: 808960 | Author: guo | Hits:

[VHDL-FPGA-Verilog] 8b10b_encdec

Description: VHDL写的8B10B编码解码器的实现，在Xilinx平台通过验证。-Written in VHDL coding 8B10B decoder realize, in the Xilinx platform validated.
Platform: | Size: 70656 | Author: 张开文 | Hits:

[VHDL-FPGA-Verilog] PWM

Description: 脉冲宽度调制，VHDL代码编写，包括QUARTUSII和MODELSIM工程以及testbench-Pulse width modulation, VHDL coding, including QUARTUSII and ModelSim engineering and Testbench
Platform: | Size: 348160 | Author: horse | Hits:

[VHDL-FPGA-Verilog] 8051forxilinx

Description: 这是一个基于xilinx平台的8051处理器文件，用VHDL代码编写-This is a platform based on Xilinx 8051 processor document, using VHDL coding
Platform: | Size: 4520960 | Author: 王龙 | Hits:

[Other] vhdl-for-synthesis

Description: VHDL for synthesis for vhdl coding -VHDL for synthesis for vhdl coding ....
Platform: | Size: 565248 | Author: BURAK | Hits:

[VHDL-FPGA-Verilog] shift_register

Description: shift register it is shifte register for vhdl coding
Platform: | Size: 201728 | Author: han | Hits:

[VHDL-FPGA-Verilog] steppermotordrive_latest.tar

Description: stepper motor control through vhdl coding
Platform: | Size: 10240 | Author: sridhar | Hits:

[VHDL-FPGA-Verilog] 12_coding_guidelines

Description: VHDL代码编写规范与风格，XILINX培训用教材，WORD文档的，写得特好，只不过是E文的-VHDL coding and style norms, XILINX training materials, WORD documents, and written special good, but is E-man
Platform: | Size: 154624 | Author: 邓子龙 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: design of vhdl coding for genetic algorithm
Platform: | Size: 237568 | Author: ram kumar | Hits:

[VHDL-FPGA-Verilog] Coding

Description: 这是用VHDL语言编写的4位比较器，用了三种描述进行编写-This is the VHDL language with the 4-bit comparator, used to prepare three kinds of descriptions
Platform: | Size: 4096 | Author: wilson | Hits:

[VHDL-FPGA-Verilog] JPEG

Description: 本文首先介绍了静态图像压缩（JPEG）编码算法的基本原理、压缩的实现过程及其重要过程的离散余弦变换（DCT）算法的实现原理及软件实现的例程，其次着重介绍了压缩过程中的DCT、量化和编码三个重要步骤的实现原理。-This paper describes the static image compression (JPEG) coding algorithm is the basic principle of compression process of the implementation process and its important discrete cosine transform (DCT) Algorithm theory and software implementation of the routines, followed by highlights of the compression process DCT, quantization and encoding steps in the realization of three important principles.
Platform: | Size: 41984 | Author: xuai | Hits:

[VHDL-FPGA-Verilog] Verilog--coding--style

Description: Verilog可综合代码编写风格介绍。属于HW中央逻辑开发部的绝密资料，加上本人的总结而成。喷血推荐。-The coding style of Verilog language. It is very useful for verilog system developer
Platform: | Size: 448512 | Author: liangyao | Hits:

[VHDL-FPGA-Verilog] Digital-FM-transmitter-VHDL-coding

Description: it is VHDL code for Digital fm modem transmitter block.
Platform: | Size: 10240 | Author: anbu | Hits:

[VHDL-FPGA-Verilog] vhdl-coding-procedures

Description: vhdl coding procedures 是在quartusII 下用VHDL编写的 包括了双极性码编hdb3码 和用3位二进制码编hdb3码 -vhdl coding procedures in quartusII prepared under the covers with the VHDL code compilation hdb3 bipolar code and binary code compiled using three hdb3 code
Platform: | Size: 2048 | Author: zln | Hits:

[VHDL-FPGA-Verilog] SPANNING TREE ADDER 27-bit VHDL

Description: 27-bit spanning tree adder written in VHDL coding
Platform: | Size: 189982 | Author: spgp1306 | Hits:
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