Search - vhdl code to lcd display

[Other resource] DJDPLJ_T

Description: 本VHDL源代码由顶层模块、测频模块、驱动模块、计算模块、LCD显示模块、复位模块组成，能精确检测从1--100M频率，误差极小且恒定。-the VHDL source code from the top module, measuring frequency module, driver modules, modules, LCD display module, reduction modules, can be used to accurately detect from 1 -- 100M frequency, constant and very small errors.
Platform: | Size: 481224 | Author: 刘刚 | Hits:

[VHDL-FPGA-Verilog] DJDPLJ_T

Description: 本VHDL源代码由顶层模块、测频模块、驱动模块、计算模块、LCD显示模块、复位模块组成，能精确检测从1--100M频率，误差极小且恒定。-the VHDL source code from the top module, measuring frequency module, driver modules, modules, LCD display module, reduction modules, can be used to accurately detect from 1-- 100M frequency, constant and very small errors.
Platform: | Size: 481280 | Author: 刘刚 | Hits:

[VHDL-FPGA-Verilog] LCD1602

Description: LCD1602显示源代码 1。源文件保存在src目录，QII的工程文件保存在Proj目录； 2。程序实现的功能是标准的16×2字符型液晶模块上显示字符串； 3-LCD1602 display the source code 1. Source file stored in the src directory, QII the project file stored in the directory Proj 2. Realize the function of the procedure is a standard 16 × 2 character LCD module to display the string 3
Platform: | Size: 716800 | Author: 张海风 | Hits:

[VHDL-FPGA-Verilog] UP3_CLOCK

Description: 在UP3开发板上已经验证过的VHDL代码。精确到十分之一秒，具有闹钟，整点报时，时间可重新设置等功能，在LCD1602上显示。绝对推荐，比网上其他类似代码功能要全而且经过验证。-In the UP3 development board has been verified VHDL code. Accurate to one-tenth of seconds, with the alarm clock, the whole point timekeeping, time and other functions can be re-instated in the LCD1602 display. Absolutely recommended online than other similar features to the entire code and verified.
Platform: | Size: 728064 | Author: kehan | Hits:

[VHDL-FPGA-Verilog] LCDshow

Description: 基于VHDL的LCD显示程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用-VHDL based on the LCD display program, including complete source code, locking pin, as well as download files documents can be directly downloaded using
Platform: | Size: 19456 | Author: 陈泽涛 | Hits:

[SCM] ps2_lcd

Description: 1、ps/2键盘输入，通过led显示ascii码 2、稍等1s可以在lcd上显示输入的字符 3、其中键盘上的backspce键是用来清屏的 4、当lcd上显示满字符时，在按下按键自动清屏，从第一行显示。-1, ps/2 keyboard input, through the led display ascii code 2, wait 1s in the lcd display characters input 3, which backspce keys on the keyboard was required to settle the screen 4, when the lcd display full of characters, the press the button automatically Qing-ping, from the first line of display.
Platform: | Size: 9216 | Author: yuan | Hits:

[SCM] LCD

Description: LCD显示的完整代码，采用Verilog编写-LCD display complete code, the use of Verilog to prepare
Platform: | Size: 405504 | Author: 陈成 | Hits:

[Technology Management] dds9851

Description: 本文主要介绍的是采用直接数字频率合成的短波信号发生器，它主要以微电脑控制部分、直接数字频率合成（DDS）部分、数字锁相环频率合成部分、背光液晶显示部分、功率放大部分等组成。该软件系统采用菜单形式进行操作，操作方便明了，增加了很多功能。它通过启动DDS后，把内存缓存区的数据送到DDS后输出相应的频率，并把数据转换为BCD码，送到液晶显示器进行显示。该系统输出稳定度、精度极高，适用于当代的尖端的通信系统和精密的高精度仪器。-This paper describes the use of direct digital frequency synthesis of short-wave signal generator, which is part of a micro-computer control, Direct Digital Synthesis (DDS) of the digital part of PLL frequency synthesizer, backlit liquid crystal display of the power amplifier, etc. composition. The menu system uses the form of software to operate, easy to operate and clear, increase in the number of features. DDS through start after the memory cache after the data to the DDS output corresponding frequency, and the data is converted to BCD code to the LCD display. The output of the system stability, high precision for cutting-edge contemporary and sophisticated communication systems high-precision instruments
Platform: | Size: 466944 | Author: xiang | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: Program VHDL is scan keypad matrix 3*3 display to LCD
Platform: | Size: 659456 | Author: pokamon | Hits:

[VHDL-FPGA-Verilog] lcd_1602

Description: 该代码是用VHDL语言写的，用来控制LCD1602液晶显示器，功能正确。-The code is written in VHDL language to control the LCD1602 LCD display, function correctly.
Platform: | Size: 5120 | Author: 王伟 | Hits:

[VHDL-FPGA-Verilog] LCD12864

Description: 利用FPGA编程实现在LCD上显示汉字，非常实用的教程，里面有详细的代码说明，修改后即可实现你的需求。-Using FPGA Programming in LCD display Chinese characters, a very useful tutorial, which has a detailed code instructions can be modified to meet your needs.
Platform: | Size: 337920 | Author: 赵琳 | Hits:

[VHDL-FPGA-Verilog] lcd.vhd

Description: 能够实现控制LCD显示的VHDL程序代码。-To achieve control of LCD display VHDL code.
Platform: | Size: 1024 | Author: 刘静 | Hits:

[VHDL-FPGA-Verilog] LCD12864

Description: 1 fpga驱动lcd液晶12864的verilog源程序 (显示英文，可以在源程序中直接修改成自己想要显示的英文) 2 引脚配置完成，程序已经测试，完全好用 3 使用的FPGA芯片是altera的max2EP2C5T1-1 fpga driver' s verilog source code 12864 lcd LCD (display in English, you can directly modify the source program into what you want displayed in English) 2-pin configuration is completed, the program has been tested, completely easy to use 3 FPGA chip is used in the altera max2EP2C5T144
Platform: | Size: 619520 | Author: pomao | Hits:

[Windows Develop] fVerrilog_Devr

Description: 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器，乘法器，多路选择器，二进制转BBCD码，加法器，减法器，简简单易懂状态机，四位比较器，7段数码管，i2c总线，lcd液晶LCD显示出来，拨码开关，串口，蜂鸣器，矩阵键盘，跑马灯，交通灯，数字时钟可直接使用。 -Friends, I Jawen. See previous upload a CPLD Development Board VHDL source code quite popular, she will Verilog source together with contribution to everyone: eight priority encoder, multipliers, multiplexers binary switch the BBCD code, adder, subtracter, simple straightforward state machine, four comparators, 7-segment LED, i2c bus, lcd LCD LCD display, DIP switch, serial port, buzzer, matrix keyboard, Marquee, traffic lights, digital clock can be used directly.
Platform: | Size: 3170304 | Author: qtzx | Hits:

[VHDL-FPGA-Verilog] lcd_phoneNumber

Description: 使用ＶＨＤＬ语言实现ｌｃｄ滚动显示电话号码的功能，对于初学ＶＨＤＬ语言与ＦＰＧＡ的工程师无疑是一个很好的入门代码！-Using VHDL language to realize LCD rolling display telephone number function, for beginners VHDL language and FPGA engineer is undoubtedly a good introduction to code!
Platform: | Size: 1024 | Author: 杜彬 | Hits:

[VHDL-FPGA-Verilog] AVA6SV2_LCD

Description: Vhdl Code for lcd 16*2 . display text and how to rotate a text in lcd with pure vhdl code
Platform: | Size: 80896 | Author: mehdi | Hits:

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[Other resource] DJDPLJ_T

[VHDL-FPGA-Verilog] DJDPLJ_T

[VHDL-FPGA-Verilog] LCD1602

[VHDL-FPGA-Verilog] UP3_CLOCK

[VHDL-FPGA-Verilog] LCDshow

[SCM] ps2_lcd

[SCM] LCD

[Technology Management] dds9851

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] lcd_1602

[VHDL-FPGA-Verilog] LCD12864

[VHDL-FPGA-Verilog] lcd.vhd

[VHDL-FPGA-Verilog] LCD12864

[Windows Develop] fVerrilog_Devr

[VHDL-FPGA-Verilog] lcd_phoneNumber

[VHDL-FPGA-Verilog] AVA6SV2_LCD

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