Search - vhdl code for elevator

[VHDL-FPGA-Verilog] DEMO22

Description: ＶＨＤＬ源程序，ＭＡＸＰＬＵＳ　环境下运行，电梯控制系统-VHDL source code, under Operation Converter, elevator control system
Platform: | Size: 598016 | Author: liu | Hits:

[Other] 12121213

Description: 16层电梯 vhdl模拟代码非常完整-16-Elevator vhdl very complete simulation code
Platform: | Size: 6144 | Author: md | Hits:

[VHDL-FPGA-Verilog] lift_VHDLDocument

Description: 用VHDL描述的电梯运行程序，代码注释很详细，希望对大家有帮助-VHDL description of the elevator used to run programs, code comment in great detail, I hope all of you help
Platform: | Size: 162816 | Author: ninghuiming | Hits:

[Graph program] lift

Description:
Platform: | Size: 8192 | Author: qlz | Hits:

[VHDL-FPGA-Verilog] lift

Description: 采用vhdl语言的电梯控制器源代码，能够实现报警，等待，并采用了标准的最优电梯运动路线。-Using VHDL language elevator controller source code, to realize the police, waiting, and the optimal use of the standard line of lift movement.
Platform: | Size: 2048 | Author: wriuwru | Hits:

[VHDL-FPGA-Verilog] lift_code_verilog

Description: 实现一个4层楼的单电梯控制系统。门可以自动开关也可以手动开关。代码可综合，无多驱动现象。-Realize a 4-story single-elevator control system. Door can automatically switch can also manually switch. Code can be integrated, no more than drive the phenomenon.
Platform: | Size: 3072 | Author: 幻婳 | Hits:

[VHDL-FPGA-Verilog] chengxu

Description: 关于频率计程序的设计，LCD控制程序，PSK调制解调的控制程序，MSK调制解调控制程序，电梯控制程序，TLC5510控制程序，基带码发生器程序，电子琴程序，自动售货机程序，电子时钟程序，步进电机控制定位系统，波形发生器，出租车计价器，ADCO809-Procedures regarding the design of frequency meter, LCD control procedures, PSK modulation and demodulation of the control procedures, MSK modulation and demodulation control procedures, procedures for elevator control, TLC5510 control procedures, base-band code generator procedures, organ procedures vending machine procedures, electronic clock procedures, stepper motor control of positioning systems, waveform generator, Taximeter, ADCO809
Platform: | Size: 1277952 | Author: chenjy | Hits:

[VHDL-FPGA-Verilog] dianti

Description: 电梯的VHDL设计，上面有源代码，希望对大家有用-VHDL elevator design, source code above, I hope useful for everyone
Platform: | Size: 162816 | Author: 崔 | Hits:

[VHDL-FPGA-Verilog] lift.vhd

Description: 用VHDL实现了电梯的模拟程序，实现了自动判断楼层，然后根据客户需求和楼层最近原则，实现自动判断上下行，还有报警，强制开门等功能-Achieved using VHDL elevator simulation program, to determine the realization of an automatic floor, and then based on the principle of demand and the floor recently, automatically determine the next line, as well as alarm, forced open the door and other features ~ ~
Platform: | Size: 1024 | Author: 董灏 | Hits:

[VHDL-FPGA-Verilog] Vhdl1

Description: Top Level VHDL Code -- simulate the relatively slow progress of an elevator car by dividing the -- clock down by an outrageously high number and scanning the car registers for -- an elevator s next -- (normally the signals used below would be IO pins on the chip, but we have -- no physical elevator, so this is a kind of "diagnostic mode")-Top Level VHDL Code -- simulate the relatively slow progress of an elevator car by dividing the -- clock down by an outrageously high number and scanning the car registers for -- an elevator s next -- (normally the signals used below would be IO pins on the chip, but we have -- no physical elevator, so this is a kind of "diagnostic mode")
Platform: | Size: 3072 | Author: Victor | Hits:

[VHDL-FPGA-Verilog] dianti

Description: FPGA的电梯控制程序，用vhdl语言实现电梯的控制的代码-FPGA elevator control program, using vhdl language implementation code for the control of the elevator
Platform: | Size: 3072 | Author: 萤火虫 | Hits:

[Software Engineering] VHDL_fire_alarm_detection

Description: vhdl source code of fire detection system/fire alarm system especially for high rise building? This among the requirement :- according to my "fire detection system for tall building" project by using Spartan 3E FPGA, the vhdl program need to include all of dis specification:- First of all, we ll put sensor/smoke detector each floor in the tall building. 1) alarm ll activated if the sensor/smoke detector sense a fire 2)at the same time, the actuator will activate in order to control such a elevator and any other machines in the building. 3)the controller will display which floor caught by fire and the sensor/smoke detector initial or current temperature. 4)If there is false alarm, we can stop it by push the reset button .-vhdl source code of fire detection system/fire alarm system especially for high rise building? This is among the requirement :- according to my "fire detection system for tall building" project by using Spartan 3E FPGA, the vhdl program need to include all of dis specification:- First of all, we ll put sensor/smoke detector each floor in the tall building. 1) alarm ll activated if the sensor/smoke detector sense a fire 2)at the same time, the actuator will activate in order to control such a elevator and any other machines in the building. 3)the controller will display which floor caught by fire and the sensor/smoke detector initial or current temperature. 4)If there is false alarm, we can stop it by push the reset button .
Platform: | Size: 1024 | Author: subin | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: For the animal file: we built a system that took in a UAC code and output if the animals need vaccines and if we are in danger of being eaten Seven_segment Clock_Design : built a clock State_machine: RoboRacer game (r9-bit LFSR) For the Elevator assignment: built an elevator with 6 floor -For the animal file: we built a system that took in a UAC code and output if the animals need vaccines and if we are in danger of being eaten Seven_segment Clock_Design : built a clock State_machine: RoboRacer game (r9-bit LFSR) For the Elevator assignment: built an elevator with 6 floor
Platform: | Size: 1785856 | Author: Michael Ng | Hits:

[VHDL-FPGA-Verilog] Control-Lift

Description: 本程序是用来控制电梯的VHDL代码，没有通过具体调试，但是可以作为学习的参考。-This procedure is used to control the elevator VHDL code, no specific debugging, but can be used as a reference for learning.
Platform: | Size: 334848 | Author: 工程师 | Hits:

[VHDL-FPGA-Verilog] elevator-controller-VHDL

Description: 电梯控制器程序设计与仿真，本文为DOC文档，附有源码和仿真波形-The elevator controller programming and simulation, this paper for the DOC document, attached to the source code and simulation waveform
Platform: | Size: 166912 | Author: | Hits:

[VHDL-FPGA-Verilog] Elevator

Description: Simple vhdl code for elevator
Platform: | Size: 9216 | Author: Sam | Hits:

[VHDL-FPGA-Verilog] final

Description: this vhdl code is for a 4th floor elevator control.
Platform: | Size: 1024 | Author: asd | Hits:

[Other] ascensseur_etats

Description: elevator code in vhdl first floor and second floor simple code that give for initiation for vhdl
Platform: | Size: 1024 | Author: amine1928 | Hits:

[VHDL-FPGA-Verilog] 1

Description: VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，序列检测器的设计，一般状态机等等。(VHDL code, some textbooks for small programs. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3 priority encoder, 8 choose 1, BCD-7 segment display decoder truth table, half adder, Moore state machine, digital frequency meter, digital clock, sequence detector design, general state machine etc..)
Platform: | Size: 453632 | Author: zidting | Hits:

[VHDL-FPGA-Verilog] 2

Description: VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字时钟，序列检测器的设计，一般状态机等等。(VHDL code, some textbooks for small programs. It includes 3 line -8 line decoder, 4 selector 1 selector, 6 elevator, 8 line -3 encoder, 8 line -3 line priority encoder, 8 select 1, BCD-7 segment display decoder truth table, half adder, Moore state machine, digital clock, sequence detector design, general state machine and so on.)
Platform: | Size: 454656 | Author: zidting | Hits:

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[VHDL-FPGA-Verilog] DEMO22

[Other] 12121213

[VHDL-FPGA-Verilog] lift_VHDLDocument

[Graph program] lift

[VHDL-FPGA-Verilog] lift

[VHDL-FPGA-Verilog] lift_code_verilog

[VHDL-FPGA-Verilog] chengxu

[VHDL-FPGA-Verilog] dianti

[VHDL-FPGA-Verilog] lift.vhd

[VHDL-FPGA-Verilog] Vhdl1

[VHDL-FPGA-Verilog] dianti

[Software Engineering] VHDL_fire_alarm_detection

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] Control-Lift

[VHDL-FPGA-Verilog] elevator-controller-VHDL

[VHDL-FPGA-Verilog] Elevator

[VHDL-FPGA-Verilog] final

[Other] ascensseur_etats

[VHDL-FPGA-Verilog] 1

[VHDL-FPGA-Verilog] 2

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