Description: 在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号是最重要的信号之一。 下面我们介绍分频器的 VHDL 描述，在源代码中完成对时钟信号 CLK 的 2 分频， 4 分频， 8 分频， 16 分频。 这也是最简单的分频电路，只需要一个计数器即可。-in digital circuits, and often the need for higher frequency for the clock frequency operation, the lower frequency clock signal. We know that the hardware circuit design clock signal is the most important one of the signals. Below us Divider VHDL description of the source code for the completion of the clock signal CLK frequency of 2 hours, 4 frequency, frequency of 8 hours, 16 minutes frequency. This is the most simple-frequency circuit, only one counter will be. Platform: |
Size: 1435 |
Author:卢吉恩 |
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Description: 除法器的设计本文所采用的除法原理是：对于八位无符号被除数A，先对A转换成高八位是0低八位是A的数C，在时钟脉冲的每个上升沿C 向左移动一位，最后一位补零，同时判断C的高八位是否大于除数B，如是则C的高八位减去B，同时进行移位操作，将C的第二位置1。否则，继续移位操作。经过八个周期后，所得到的C的高八位为余数，第八位为商。从图(1)可清楚地看出此除法器的工作原理。此除法器主要包括比较器、减法器、移位器、控制器等模块。-Divider design used in this paper, the principle of division is: For the eight unsigned dividend A, the first of A into the high-low 8 0 8 is the A number of C, in each clock rising edge to the left C Mobile One, and finally a zero, at the same time to determine whether C is greater than the high-8 divisor B, so is the high C 8 minus B, at the same time shift operation, the location will be C s second one. Otherwise, continue to shift operation. After eight cycles, received a high C for more than eight the number of eighth place for the business. From Figure (1) can clearly see that the divider works. This mainly includes divider comparators, subtraction, and shifter, controller modules. Platform: |
Size: 1024 |
Author:lyy |
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Description: 分频器的vhdl描述，在源代码中完成对时钟信号CLK的2分频,4分频,8分频,16分频-Divider vhdl description of the source code at the completion of the CLK clock signal frequency of 2 hours, 4 minutes frequency, frequency of 8 hours, 16 minutes frequency Platform: |
Size: 1024 |
Author:LS |
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Description: This code contains the simple program that can be used for the clock divider to set any desireable clock from the master clock. Platform: |
Size: 1024 |
Author:Shahzad |
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Description: VHDL code for clock divider circuit. There are two modules: one output divide by 4 and other outputs divide by 6 Platform: |
Size: 1024 |
Author:zpatel |
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Description: Package consists of two pdf files:
i)cdr project: theory and implementation of vhdl
ii)I2C bus controller: xilinx implementation of uC interface on CPLD
Package consists of 7 vhdl files:
string_detector: detects the continuous string of 111
led_driver: code for running leds on dvpt board
clk_div: clock divider circuitry (component for led code)
mem: memory component for led code
ram_dual: dual port ram implementation-Package consists of two pdf files:
i)cdr project: theory and implementation of vhdl
ii)I2C bus controller: xilinx implementation of uC interface on CPLD
Package consists of 7 vhdl files:
string_detector: detects the continuous string of 111
led_driver: code for running leds on dvpt board
clk_div: clock divider circuitry (component for led code)
mem: memory component for led code
ram_dual: dual port ram implementation
Platform: |
Size: 4604928 |
Author:Sharav |
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