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[VHDL-FPGA-Verilog] FIR低通滤波器部分模块

Description: 一个FIR低通滤波器,最小阻带衰减-30db,带内波动小于1db．用MAXPLUS2设计与仿真。-This is a FIR LPF, with-30dB in stop-band and sigma is less than 1dB. It is designed and simulated on MAXPLUS2.
Platform: | Size: 5120 | Author: 吴健宇 | Hits:

[VHDL-FPGA-Verilog] qqq

Description: 数字滤波器的vhdl源代码.在quartus上运行过,里面还有matlab的仿真文件.-Digital filter of the VHDL source code. In Quartus run-off, along with the simulation matlab file.
Platform: | Size: 26624 | Author: 萧勇 | Hits:

[VHDL-FPGA-Verilog] Digitalfilter

Description: 一篇基于FPGA的数字滤波器的小论文，附带有VHDL源码-An FPGA-based digital filter small papers, comes with VHDL source code
Platform: | Size: 198656 | Author: 蝈蝈 | Hits:

[VHDL-FPGA-Verilog] digital_filter

Description: 数字滤波器VHDL源码，在matlab下仿真-Digital filter VHDL source code, under the simulation in matlab
Platform: | Size: 26624 | Author: ltlt | Hits:

[Other] VerilogHDL

Description: 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点 结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合 利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure and the basic hardware features, a brief introduction of the FIR filter the way to achieve the advantages and disadvantages of combining Altera s Stratix series of characteristics of the product, with a MAC based on the 8-order FIR digital filter design For example, given the use of Verilog hardware description language for digital logic design process and methods, and Quartus Ⅱ integrated development environment, prepared HDL code, for comprehensive utilization of Quartus Ⅱ emulator internal design so the impulse response simulation and verification.
Platform: | Size: 79872 | Author: sundan | Hits:

[VHDL-FPGA-Verilog] iir

Description: 数字信号处理的fpga实现，用VHDL语言编程实现IIR滤波器-Digital signal processing to achieve the FPGA, using VHDL language programming to achieve IIR filter
Platform: | Size: 1024 | Author: songjunmin | Hits:

[Modem program] turtorial1

Description: matlab code for digital up conversion filter and the comand to generate the corresponding vhdl
Platform: | Size: 1024 | Author: ahmed | Hits:

[VHDL-FPGA-Verilog] FPGArealiztionofdigitalsignalprocessing

Description: 数字信号处理FPGA实现 实用程序和文件,有sine.exe ---输入宽度。输出对应的正弦波表 mif文件 csd.exe --- 寻找整数和分数的标准有符号数字量（canonical signed digit ，CSD）表达式程序 fpinv.exe --- 倒数计算浮点数表的程序 dagen.exe ---分布式算法文件生成HDL" onclick="tagshow(event)" class="t_tag">VHDL代码的程序 cic.exe ---CIC滤波器计算参数的程序 -Digital Signal Processing FPGA realization of practical procedures and documents, there are sine.exe--- input width. Sine wave output of the corresponding csd.exe--- Table mif file to find the integer and fractional number of the volume of standard symbols (canonical signed digit, CSD) Expression Programming fpinv.exe--- countdown procedures for calculation of floating-point form dagen.exe--- documents distributed algorithm to generate HDL " onclick =" tagshow (event) " class =" t_tag " > VHDL program code cic.exe--- CIC filter process parameters
Platform: | Size: 260096 | Author: kevin | Hits:

[source in ebook] Finiteimpulseresponsefirfilter

Description: This code is a VHDL based code for FIR filter.A finite impulse response (FIR ) filter is a type of a digital filter. The impulse response, the filter s response to a Kronecker delta input, is finite because it settles to zero in a finite number of sample intervals.
Platform: | Size: 44032 | Author: kumar | Hits:

[VHDL-FPGA-Verilog] fir

Description: 数字电路设计中的，fir滤波器设计，我做的是8位宽的，利用vhdl实现，附带了完整的代码，报告，我没有对我的信息进行删除，是希望大家能够诚实的利用这个代码，提高自身本领。-Digital circuit design, fir filter design, I am doing is 8 bits wide, using vhdl implementation, with a complete code, the report, I did not delete my information in the hope that we can use this code for an honest to improve their skills.
Platform: | Size: 3322880 | Author: de de | Hits:

[VHDL-FPGA-Verilog] IIR(vhdl)

Description: 基于fpga的数字滤波器设计的vhdl源代码-Fpga digital filter design based on the vhdl source code
Platform: | Size: 7168 | Author: sunnyhp | Hits:

[VHDL-FPGA-Verilog] filter1

Description: 题为基于CSD编码的FIR数字滤波器设计.该滤波器具有线性相位,系数减半.采用VHDL语言编写.是我们EDA课程的作业,得了优.希望对大家有用-Entitled based on CSD code FIR digital filter design. That the filters have linear phase, coefficient half. Using VHDL language. Is the EDA program operations, got excellent. Hope it would be useful
Platform: | Size: 13312 | Author: 万勇 | Hits:

[VHDL-FPGA-Verilog] code

Description: it is the collection of the modules involved inthe design of digital fm.the code coves the key components like numerically controlled oscillator, loop filter, fir filter ,phase detector along with the complete cicuit implementation of the digital fm and the test bench of it.
Platform: | Size: 5120 | Author: syamprasad | Hits:

[VHDL-FPGA-Verilog] decimator

Description: Digital filter in delta-sigma ADC. But only work for RTL code now. Still have bugs in gate-level simulation.
Platform: | Size: 1024 | Author: DrCheese | Hits:

[VHDL-FPGA-Verilog] FIR-LOOP-

Description: 数字接收机中的FIR滤波器，环形滤波器设计参考,VHDL代码-the FIR filter， loop filter design in a digital receiver,vhdl code
Platform: | Size: 1024 | Author: rickdecent | Hits:

[VHDL-FPGA-Verilog] FIR-filter-VHDL-code

Description: 基于FPGA的17阶FIR滤波器VHDL代码。文件附带了FIR数字滤波器理论的介绍。-FPGA-based 17-order FIR filter VHDL code. File with the FIR digital filter theory introduction.
Platform: | Size: 919552 | Author: 周鑫 | Hits:

[source in ebook] Chapter_2

Description: 《FPGA数字滤波器设计》第二章源码，包含VHDL代码和Matlab仿真代码-" The second chapter of the the FPGA digital filter design source code contains the VHDL code and Matlab simulation code
Platform: | Size: 7540736 | Author: liuguagnquan | Hits:

[matlab] xiaosong-fpga

Description: FIR数字滤波，亲自测试，都是源码，希望可以帮到大家，谢谢，谢谢！大家要好好学习呀，学习好VHDL(FIR digital filter, personally tested, are source code, and I hope to help you, thank you, thank you! We should study hard, good study, VHDL)
Platform: | Size: 6714368 | Author: dasdsadas | Hits:

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