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[VHDL-FPGA-Veriloganjian

Description: 按键输入模块(key): --可编程延时发生器(数字同步机)的前端输入模块:0-9十个数字键按键输入模块原型 --前端模块:消抖 --对i0-i9十个输入端的两点要求: --(1)输入端要保证一段时间的稳定高电平 --(2)不能同时按下两个或多于两个的键 --后级模块:1、编码;2、可变模计数器 --编码模块:8线-4线(0-8 BCD码) --可变模计数器模块:以编码模块输出的32位BCD码为模值-button input module (key) :-- programmable delay generator (digital synchronous machine) the front-end input module : 0-2-9 10 numeric keys keys input module prototype-- front-end module : Consumers quiver-- the domain-Makes 10 input of the two requirements :-- (a) input to ensure a period of stability to I-- (2) can not be pressed together two or more two keys-- after class modules : one, coding; 2, variable Die counter-- Coding modules : 8-to-four (0-8 BCD)-- Variable Mode counter modules : coding module output to the 32 BCD value to Die
Platform: | Size: 2048 | Author: 汪汪 | Hits:

[SCMVHDL范例

Description: 最高优先级编码器 8位相等比较器 三人表决器(三种不同的描述方式) 加法器描述 8位总线收发器:74245 (注2) 地址译码(for m68008) 多路选择器(使用select语句) LED七段译码 多路选择器(使用if-else语句) 双2-4译码器:74139 多路选择器(使用when-else语句) 二进制到BCD码转换 多路选择器 (使用case语句) 二进制到格雷码转换 双向总线(注2) 汉明纠错吗译码器 三态总线(注2) 汉明纠错吗编码器 解复用器 -highest priority encoder, compared to eight for phase three of the vote (the description of three different ways) Adder Description eight bus Transceivers : 74,245 (Note 2) address decoder (for m68008) Multiple choice (use select statement) LED paragraph 107 of decoding multiple choice ( use if-else statements) 2-4 dual decoder : over 74,139 road choice (use when-else statements) of the binary conversion BCD multiple choice (use case statement) binary Gray code conversion to a two-way bus (Note 2)? Hamming error correction decoder three-state Bus (Note 2)? Hamming error correction encoder demultiplexer
Platform: | Size: 43008 | Author: kerty | Hits:

[VHDL-FPGA-Verilogcount16

Description: count16.vhd 16位BCD计数器VHDL源程序-count16.vhd 16 BCD counter VHDL source
Platform: | Size: 1024 | Author: 杨奎元 | Hits:

[MPIadd_16_bcd

Description: 此程序采用VHDL语言,完成在16位十六进制加法器的基础上将输出进行BCD码转换,实现输出是BCD码的16位二进制加法器-This procedure using VHDL language, completed in 16-bit hexadecimal adder based on output BCD code conversion, the realization of output is BCD code of 16 binary adder
Platform: | Size: 1024 | Author: 韩善华 | Hits:

[VHDL-FPGA-Verilogadd_32_bcd

Description: 此程序采用VHDL语言,完成在32位十六进制加法器的基础上将输出进行BCD码转换,实现输出是BCD码的32位二进制加法器-This procedure using VHDL language, completed in 32-bit hexadecimal adder based on output BCD code conversion, the realization of output is BCD code of 32 binary adder
Platform: | Size: 1024 | Author: 韩善华 | Hits:

[Otherbcd

Description: 实现bcd码与二进制码之间的相互转换功能,小于9时不变,高于九时加6功能-The realization of bcd code and binary code conversion function between, less than 9 am the same, higher than the 6 function plus 9:00
Platform: | Size: 7168 | Author: 汤仙君 | Hits:

[VHDL-FPGA-VerilogLCDshow

Description: 基于VHDL的LCD显示程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用-VHDL based on the LCD display program, including complete source code, locking pin, as well as download files documents can be directly downloaded using
Platform: | Size: 19456 | Author: 陈泽涛 | Hits:

[Otherbinarytobcd

Description: 实现二进制到BCD的转换,相关算法可参考相关文档资料-convert binary number to BCD
Platform: | Size: 3072 | Author: CoCo | Hits:

[SCMbinarytobcd_arithmetic

Description: Binary to BCD arithmetic. 这东西真不错-Binary to BCD arithmetic. This is something really good
Platform: | Size: 3072 | Author: Reguse | Hits:

[VHDL-FPGA-Verilogbin2bcd

Description: Binary to BCD converter
Platform: | Size: 1024 | Author: Natacho | Hits:

[Windows Developbcd

Description: vhdl编写的将二进制转BCD码的程序.直接源代码,适合新手编程,语法学习-BCD
Platform: | Size: 202752 | Author: yjh | Hits:

[VHDL-FPGA-VerilogMultBCD

Description: Multiplier BCD - vhdl-Multiplier BCD- vhdl
Platform: | Size: 303104 | Author: svxiuh | Hits:

[VHDL-FPGA-Verilogbcd

Description: EDA 十进制计数器、BCD VHDL源代码-EDA decimal counter VHDL source code
Platform: | Size: 1024 | Author: 啊毛 | Hits:

[VHDL-FPGA-VerilogBCD

Description: vhdl写的十进制转BCD的源代码-vhdl decimal to BCD written the source code~~~~~~~~~~~~~~~~~
Platform: | Size: 123904 | Author: zll | Hits:

[assembly languagebinarytobcd

Description: binary to bcd which converts 8bit binary input to bcd -binary to bcd which converts 8bit binary input to bcd
Platform: | Size: 3072 | Author: suri | Hits:

[VHDL-FPGA-VerilogSeven-Segment-Decoder

Description: 用VHDL语言在FPGA上实现将十进制bcd码转换成七段led显示码-FPGA using VHDL language to achieve will be converted to decimal bcd yards led seven segment display code
Platform: | Size: 1024 | Author: 吴金通 | Hits:

[VHDL-FPGA-Verilogxq_Test7

Description: VHDL语言编写一个BCD计数器并在七段显示数码管上显示的程序,实现了动态扫描,而且很好用-VHDL language a BCD counter and in the seven-segment display digital tube display process to achieve a dynamic scanning, and it just works
Platform: | Size: 144384 | Author: 夏强 | Hits:

[VHDL-FPGA-VerilogBCD

Description: 基于VHDL语言,实现二进制转换为BCD码。-Based on the VHDL language, to achieve a binary code is converted to BCD.
Platform: | Size: 3072 | Author: xiaokun | Hits:

[VHDL-FPGA-VerilogBCD

Description: BCD码和二进制之间的转化,FPGA中的实现,内附原理及代码!-BCD conversion between binary code and, FPGA Realization of, containing principles and code!
Platform: | Size: 165888 | Author: rbj | Hits:

[VHDL-FPGA-Verilog2-Decimal-BCD-Decoder

Description: 二-十进制BCD译码器,就是用VDHL编写的将二进制转化为十进制的BCD译码器-2- Decimal BCD Decoder, is to use VDHL written into the binary decimal BCD decoder
Platform: | Size: 1024 | Author: 易云箫 | Hits:
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