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[Other resource] xia_yuwen_verilog_PPT

Description: 北航夏雨闻的Verilong课件，与夏雨闻写的Verilog数字系统设计教程配套
Platform: | Size: 514008 | Author: xiaotian | Hits:

[Other resource] 16bitadder

Description: 16位快速加法器verilong实现，很值得一看~
Platform: | Size: 2832 | Author: 屈开 | Hits:

[Other resource] verilog

Description: 有例程和VERILONG语言的描述,可能对初学者有用.如果谁有好的VERILONG自己写的程序,请大家上传一些,借鉴一下
Platform: | Size: 113606 | Author: 李 | Hits:

[assembly language] miaobiao

Description: 数字秒表，有分，秒，毫秒，精确度极高。使用verilong语言，程序短小精炼，非常值得参考。
Platform: | Size: 46130 | Author: 李立 | Hits:

[SourceCode] verilog例子大全

Description: 包含各种verilong HDL语言的编程源代码，全加器，计数器，选择器，加法器，波形发生器等以及阻塞赋值非阻塞赋值的使用例子，七段数码管显示译码器等等
Platform: | Size: 114543 | Author: lan19891028@163.com | Hits:

[VHDL-FPGA-Verilog] xia_yuwen_verilog_PPT

Description: 北航夏雨闻的Verilong课件，与夏雨闻写的Verilog数字系统设计教程配套-BUAA Xiayu Verilong heard courseware, and Xia Yu Wen wrote Verilog Digital System Design Tutorial support
Platform: | Size: 514048 | Author: xiaotian | Hits:

[VHDL-FPGA-Verilog] 16bitadder

Description: 16位快速加法器verilong实现，很值得一看~
Platform: | Size: 3072 | Author: 屈开 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 有例程和VERILONG语言的描述,可能对初学者有用.如果谁有好的VERILONG自己写的程序,请大家上传一些,借鉴一下-Have routines and VERILONG description language may be useful for beginners. If good VERILONG who write their own procedures, please upload some U.S. learn from you
Platform: | Size: 113664 | Author: 李 | Hits:

[assembly language] miaobiao

Description: 数字秒表，有分，秒，毫秒，精确度极高。使用verilong语言，程序短小精炼，非常值得参考。-Digital stopwatch, who, seconds, milliseconds, a very high accuracy. Verilong language used, procedures short refining, very worth considering.
Platform: | Size: 46080 | Author: 李立 | Hits:

[SCM] 29becbce-7f76-454c-9f85-fb6138f83375

Description: cpu IP 核设计的verilong代码-cpu IP core design code verilong
Platform: | Size: 104448 | Author: mypudn | Hits:

[VHDL-FPGA-Verilog] DA_TLC5620

Description: 用verilong hdl语言编写的数据采样程序，A/D采用的是TLC5260-Verilong hdl language used data sampling procedures, A/D using the TLC5260
Platform: | Size: 761856 | Author: 李俭 | Hits:

[VHDL-FPGA-Verilog] examples

Description: Verilong 经典例子王金明：《Verilog HDL 程序设计教程》-Wang Jinming Verilong classic example: " Verilog HDL Design Tutorial"
Platform: | Size: 21504 | Author: 朱大海 | Hits:

[VHDL-FPGA-Verilog] DE2_TV_PAL

Description: video信号pal制转vga输出，fpga verilong语言编写-fpga pal to vga ，writed in verilog
Platform: | Size: 2042880 | Author: james | Hits:

[Other Embeded program] uart

Description: fpga 串行口接收和发送程序，采用verilong语言编写-fpga uart ，receive and send include writed by verilog language
Platform: | Size: 371712 | Author: james | Hits:

[VHDL-FPGA-Verilog] verilogRS

Description: 该文件为基于fpga的RS（204.188）译码器的verilong源代码，使用的Quartus II的开发环境，已经通过编译，需要者可以自己下载在编译简历工程使用-The document is based on fpga' s RS (204.188) decoder verilong source code, use the Quartus II development environment, has been compiled by the need to download the compiler can resume their work using
Platform: | Size: 13312 | Author: bobo | Hits:

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[Other resource] xia_yuwen_verilog_PPT

[Other resource] 16bitadder

[Other resource] verilog

[assembly language] miaobiao

[SourceCode] verilog例子大全

[VHDL-FPGA-Verilog] xia_yuwen_verilog_PPT

[VHDL-FPGA-Verilog] 16bitadder

[VHDL-FPGA-Verilog] verilog

[assembly language] miaobiao

[SCM] 29becbce-7f76-454c-9f85-fb6138f83375

[VHDL-FPGA-Verilog] DA_TLC5620

[VHDL-FPGA-Verilog] examples

[VHDL-FPGA-Verilog] DE2_TV_PAL

[Other Embeded program] uart

[VHDL-FPGA-Verilog] verilogRS

[VHDL-FPGA-Verilog] lcd

[VHDL-FPGA-Verilog] ScanKey

[VHDL-FPGA-Verilog] ps2

[VHDL-FPGA-Verilog] 1602

[VHDL-FPGA-Verilog] lift-verilogHDL

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