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[VHDL-FPGA-Verilog] 不用IP核设计乘法器

Description: VerilogHDL语言实现 不用IP核设计乘法器。(VerilogHDL language, do not use IP core design multiplier.)
Platform: | Size: 405504 | Author: 朱朱8 | Hits:

[VHDL-FPGA-Verilog] FPGA读写SDRAM的实例

Description: FPGA对SDRAM进行读写测试程序，亲测有效无误。(FPGA reads and writes test programs for SDRAM.)
Platform: | Size: 19928064 | Author: 蠢月月 | Hits:

[VHDL-FPGA-Verilog] VerilogHDL的135个经典设计实例

Description: Verilog HDL编程设计学习程序例子，含详细说明(Verilog HDL programming design learning examples, including detailed description)
Platform: | Size: 157696 | Author: 斯文小卡 | Hits:

[Other] VerilogHDL扫盲文

Description: verilog扫盲文，帮助初学者大概了解verilog的最基本概况(Verilog scan Braille, to help beginners understand about the most basic situation of Verilog)
Platform: | Size: 3334144 | Author: joinlaber | Hits:

[VHDL-FPGA-Verilog] aes

Description: AES FPGA verilogHDL实现(AES hardware implementation)
Platform: | Size: 36864 | Author: 猪在飞 | Hits:

[VHDL-FPGA-Verilog] VerilogHDL硬件描述语言

Description: Verilog语言入门教程，详细讲述了Verilog语法和应用(Verilog language introductory course, detailing the Verilog syntax and Application)
Platform: | Size: 3091456 | Author: Arwen_yuan | Hits:

[VHDL-FPGA-Verilog] eetop.cn_Verilog HDL入门（第三版）【夏宇闻】

Description: veriloghdl数字设计与综合夏宇闻翻译(dgfsdghfhsgdfhgfddfghdfh)
Platform: | Size: 4855808 | Author: petpat | Hits:

[Other] VerilogHDL那些事儿_建模篇（for DB4CE6）

Description: FPGA那些事的电子书籍，有需要的，可以自行下载(FPGA electronic books that are needed, can be downloaded on their own)
Platform: | Size: 7195648 | Author: 记忆中的我 | Hits:

[VHDL-FPGA-Verilog] 他和它的故事 VerilogHDL之系列笔记

Description: 他和它的故事之一些对verilog实验的思考和笔记。(Some thoughts and notes on the Verilog experiment.)
Platform: | Size: 24336384 | Author: jetyeah | Hits:

[Special Effects] 8-8DCT变换verilogHDL代码

Description: DCT变换实现图像压缩及嵌入水印等,内含测试文件及DCT算法讲解(Image compression and embedding watermark by DCT transform)
Platform: | Size: 23552 | Author: 和悦 | Hits:

[VHDL-FPGA-Verilog] CNN

Description: THU微纳电子系ic设计课程大作业，使用verilog实现CNN加速器，含一层卷积和池化，仿真通过。(a CNN accelerator written in VerilogHDL, including one conv layer and one pooling layer, simulation passed)
Platform: | Size: 1805312 | Author: gothic22 | Hits:

[Decompilation] VHDL 转verilog工具

Description: 这是一款可以将VHDL转换为verilogHDL的专用工具，欢迎大家下载
Platform: | Size: 20896463 | Author: 1251602320@qq.com | Hits:
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