Search - verilog1

[Other resource] verilog1

Description: verilog具体讲解-Verilog
Platform: | Size: 468857 | Author: 飞翔之梦 | Hits:

[Other resource] verilog1

Description: 基于FPGA的多功能数字钟Verilog设计2007-06-17 21:06基本功能： 1．具有时、分、秒计数显示功能（6位数码管构成），以24小时循环为计时基准。 2. 具有调节小时、分钟的功能。 3．具有整点报时功能，整点报时的同时数码管显示闪烁提示。
Platform: | Size: 8144 | Author: aa | Hits:

Description: The Universal Asynchronous Receiver Transmitter (UART) is a popular and widely-used device for data communication in the field of telecommunication. There are different versions of UARTs in the industry.
Platform: | Size: 108361 | Author: success189858 | Hits:

[VHDL-FPGA-Verilog] verilog1

Description: verilog具体讲解-Verilog
Platform: | Size: 468992 | Author: 飞翔之梦 | Hits:

[VHDL-FPGA-Verilog] verilog1

Description: 基于FPGA的多功能数字钟Verilog设计2007-06-17 21:06基本功能： 1．具有时、分、秒计数显示功能（6位数码管构成），以24小时循环为计时基准。 2. 具有调节小时、分钟的功能。 3．具有整点报时功能，整点报时的同时数码管显示闪烁提示。 -err
Platform: | Size: 8192 | Author: | Hits:

[Other Embeded program] verilog1

Description: The Universal Asynchronous Receiver Transmitter (UART) is a popular and widely-used device for data communication in the field of telecommunication. There are different versions of UARTs in the industry.
Platform: | Size: 108544 | Author: success189858 | Hits:

[Com Port] Verilog1

Description: 写PCI总线驱动的可以看看，最近在弄PIC多串口扩展卡，大家交流一下。
Platform: | Size: 1024 | Author: 龙雨 | Hits:

[VHDL-FPGA-Verilog] Verilog1

Description: 同步字检测程序，Verilog程序，初级编程-Sync word detection procedure, Verilog program, the primary programming
Platform: | Size: 3072 | Author: 张炜 | Hits:

[VHDL-FPGA-Verilog] Verilog1

Description: Verilog教程的书籍，非常基础，适合新手，并不容易找到，写得很全面-Verilog tutorial books, very basic, suitable for novice, it is not easy to find, write a very comprehensive
Platform: | Size: 289792 | Author: 熊毅 | Hits:

[VHDL-FPGA-Verilog] verilog1

Description: 此代码实现了n进制计数器，有清零。保持还有减一计数。-This code implements the n binary counter, there is clear. Keeping it there by a count
Platform: | Size: 7168 | Author: 徐岳 | Hits:

[VHDL-FPGA-Verilog] verilog1

Description: 用verilog语言编写的6分频分频计数器。分频后用来控制蜂鸣器响，也可以修改代码做成更高分频的计数器。压缩包内也包含此分频器的modelsim仿真文件-Verilog language with 6 frequency divider counter. Frequency and used to control the buzzer sound, you can modify the code to make a higher frequency counter. Compressed package also contains this file divider modelsim simulation
Platform: | Size: 143360 | Author: 广子 | Hits:

[Embeded-SCM Develop] verilog1

Description: learning verilog chinese version-learning verilog chinese version!!!
Platform: | Size: 78848 | Author: VIJAY | Hits:

[VHDL-FPGA-Verilog] verilog1

Description: 各种verilog学习资料希望对你有帮助-Learning materials of various verilog want to help you
Platform: | Size: 60416 | Author: 林畅 | Hits:

[Other] Verilog1

Description: vverilog经典教程（pdf），适合初学者-vverilog classic tutorial (pdf), suitable for beginners
Platform: | Size: 1314816 | Author: 陆建强 | Hits:

[Other] Verilog1

Description: 实现了cic分频功能，分频系数D可变2~32，代码用verilog编写，其中输入数据写入主程序中，便于后人testbench的编写-Cic divide divider coefficient D variable from 2 to 32, the code is written in verilog input data is written to the main program, to facilitate future generations testbench preparation
Platform: | Size: 2048 | Author: yangningcong | Hits:

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[Other resource] verilog1

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[VHDL-FPGA-Verilog] VERILOG1

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