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[Com Port] verilog_UART

Description: UART verilog hdl 实现-UART Verilog HDL achieve
Platform: | Size: 3072 | Author: | Hits:

[VHDL-FPGA-Verilog] verilog_shili

Description: 计数器 锁存器 12位寄存器 带load，clr等功能的寄存器 双向脚（clocked bidirectional pin） 一个简单的状态机 一个同步状态机 用状态机设计的交通灯控制器 数据接口 一个简单的UART 测试向量（Test Bench）举例： 加法器源程序 相应加法器的测试向量test bench）-Counter latch 12 registers with load, clr functions such as two-foot register (clocked bidirectional pin) a simple state machine synchronous state machine with a state machine design data interface controller traffic lights a simple UART test vectors (Test Bench), for example: source corresponding adder adder test bench test bench)
Platform: | Size: 11264 | Author: | Hits:

[Other] u-uart

Description: UART verilog TX/RX OpenCores share
Platform: | Size: 5120 | Author: richman | Hits:

[VHDL-FPGA-Verilog] UART_for_FPGArar

Description: it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]-it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]
Platform: | Size: 5120 | Author: yasir ateeq | Hits:

[VHDL-FPGA-Verilog] uart

Description: this a verilog code about serial transmit receive.-this is a verilog code about serial transmit receive.
Platform: | Size: 4096 | Author: tri | Hits:

[VHDL-FPGA-Verilog] uartverilog

Description: Verilog Uart经典实例，适合初学者练手，建议收藏-Verilog Uart classic example, training for beginners hand, the proposed collection of
Platform: | Size: 9216 | Author: dong | Hits:

[VHDL-FPGA-Verilog] uart

Description: verilog 语言，uart 测试程序，通过串口能够测试开发板上uart芯片的好坏-uart test module with verilog langunge,it can be used to test the uart ic on your board.
Platform: | Size: 3072 | Author: chenzhi | Hits:

[VHDL-FPGA-Verilog] sim_uart

Description: uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1， 无校验位； 代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； -verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC, another Potter rate, self-modifying code can, in the alter of the FPGA, debugging through
Platform: | Size: 2048 | Author: 周西东 | Hits:

[VHDL-FPGA-Verilog] uart-code-Verilog

Description: uart控制器源码-verilog 含源码，测试向量-uart-controller-verilog-code
Platform: | Size: 10240 | Author: 李明纬 | Hits:

[VHDL-FPGA-Verilog] RS232

Description: It s combination logic for UART. Edited in verilog-HDL.
Platform: | Size: 5120 | Author: kim | Hits:

[VHDL-FPGA-Verilog] uart

Description: UART verilog 代码， 内置CPU接口方式，支持2线制和流控4线制。支持轮训和中断方式。-UART verilog source code
Platform: | Size: 15360 | Author: dingyy | Hits:

[VHDL-FPGA-Verilog] Verilog-uart

Description: Verilog状态机实现的串口串口收发模块 -Verilog state machine for uart
Platform: | Size: 1205248 | Author: fu | Hits:

[VHDL-FPGA-Verilog] zigbee_sensor

Description: ZigBee无线模块实验.rar；基于FPGA-2C35核心；博创实验箱平台。 在quartusII里面添加uart核，利用串口与主控制机相通信，获取从控制机上传感器的的温度、湿度、光敏电阻、热敏电阻等信息（其中主控制机与从控制机是通过zigbee协议通信） -ZigBee wireless module experiment rar core on the FPGA-2C35 Borch experimental box platform. Add uart nuclear quartusII inside, using the serial port with the main control machine communication, access to the sensor from the control on the temperature, humidity, photoresistors, thermistors, and other information (including the main control machine from the control machine by zigbee protocol communications)
Platform: | Size: 1388544 | Author: | Hits:

[VHDL-FPGA-Verilog] UART_Transmitter_Arch

Description: 自己编写的带有FIFO的UART串口发送模块，代码通过状态机实现，开发语言是Verilog-I have written to the FIFO UART serial transmit module code through the state machine implementation, development languages ​ ​ Verilog
Platform: | Size: 2048 | Author: wangzhongwei | Hits:

[VHDL-FPGA-Verilog] UART-finite-state-machine

Description: 基于Verilog语言的，用有限状态机实现Uart，很实用-UART design based on finite state machine
Platform: | Size: 223232 | Author: 黎杰 | Hits:

[VHDL-FPGA-Verilog] IIC_uart

Description: 本程序是用Verilog编写的，可实现IIC协议，同时联合串口uart通信，可实现pc机调试-The program is written in Verilog, enabling IIC protocol, while the United serial uart communications, enabling pc machine debugging
Platform: | Size: 760832 | Author: zhijun | Hits:

[VHDL-FPGA-Verilog] uart

Description: 用verilog实现UART串口收发。状态机形式实现，波特率可调(Use verilog to achieve UART serial transceiver. State machine form, adjustable baud rate)
Platform: | Size: 3265536 | Author: zhaodameng | Hits:

[Com Port] UART发送接收奇偶校验

Description: 状态机，串口收发，以及奇偶校验。 even_parity.v奇偶校验； receive_byte.v字节接收； send_byte.v字节发送(state machine,UART even_parity.v even parity; receive_byte.v receiving byte; send_byte.v sending byte)
Platform: | Size: 2048 | Author: 陈宇晨 | Hits:

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