Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - verilog shift

Search list

[Other resource] 八位的伪随机数产生的verilog文件

Description: 八位的伪随机数产生的verilog文件linear-feedback-shift-register-eight pseudo-random number generator in Verilog document linear-feedback - shift-register
Platform: | Size: 1837 | Author: 陈正一 | Hits:

[Communication] 伪随机序列

Description: 线形反馈移位寄存器（LFSR)是数字系统中一个重要的结构，本程序可以自动产生AHDL,VHDL,Verilog的源代码及电路原理图。程序可以运行在win98/2000/NT平台-linear feedback shift register (LFSR) digital system is an important structure, the process can be automatically generated AHDL, VHDL, Verilog source code and circuit schematics. Procedures can run on platforms win98/2000/NT
Platform: | Size: 162816 | Author: 夏沫 | Hits:

[VHDL-FPGA-Verilog] 八位的伪随机数产生的verilog文件

Description: 八位的伪随机数产生的verilog文件linear-feedback-shift-register-eight pseudo-random number generator in Verilog document linear-feedback- shift-register
Platform: | Size: 2048 | Author: 陈正一 | Hits:

[VHDL-FPGA-Verilog] magnitude

Description: Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm. -Verilog HDL : For a vector magnitude (a, b), the magnitude representation is the following : A common approach to implementing thes e arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonome tric functions of sine, cosine, magn itude, and phase using an iterative process. It i 's made up of a series of micro-rotations of the v ector by a set of predetermined cons tants, which are powers of two. Using binary ar praxiology metic, this algorithm essentially replaces m ultipliers with shift and add operations. In a Stratix
Platform: | Size: 12288 | Author: 郝晋 | Hits:

[VHDL-FPGA-Verilog] Serial_CRC

Description: CRC校验串行实现方法,verilog源码,利用反馈线性移位寄存器的方法,实现简单,适用于串行通信协议中的CRC校验.-CRC checksum method of serial realize, verilog source code, the use of linear feedback shift register method, the realization of simple serial communication protocol for the CRC checksum.
Platform: | Size: 1024 | Author: 徐亮 | Hits:

[MiddleWare] ALU

Description: 用VERILOG实现ALU，实现各种算术运算，逻辑运算，移位运算等-Realize using Verilog ALU, realize a variety of arithmetic operations, logic operations, shift operations, etc.
Platform: | Size: 1725440 | Author: 刘自强 | Hits:

[VHDL-FPGA-Verilog] divide

Description: 除法器的设计本文所采用的除法原理是：对于八位无符号被除数A，先对A转换成高八位是0低八位是A的数C，在时钟脉冲的每个上升沿C 向左移动一位，最后一位补零，同时判断C的高八位是否大于除数B，如是则C的高八位减去B，同时进行移位操作，将C的第二位置1。否则，继续移位操作。经过八个周期后，所得到的C的高八位为余数，第八位为商。从图(1)可清楚地看出此除法器的工作原理。此除法器主要包括比较器、减法器、移位器、控制器等模块。-Divider design used in this paper, the principle of division is: For the eight unsigned dividend A, the first of A into the high-low 8 0 8 is the A number of C, in each clock rising edge to the left C Mobile One, and finally a zero, at the same time to determine whether C is greater than the high-8 divisor B, so is the high C 8 minus B, at the same time shift operation, the location will be C s second one. Otherwise, continue to shift operation. After eight cycles, received a high C for more than eight the number of eighth place for the business. From Figure (1) can clearly see that the divider works. This mainly includes divider comparators, subtraction, and shifter, controller modules.
Platform: | Size: 1024 | Author: lyy | Hits:

[VHDL-FPGA-Verilog] alu

Description: 4位ALU逻辑运算单元，可进行加法、减法、逻辑运算、移位等操作。-4 ALU logical operation unit, can be additive, subtraction, logic operations, shift and other operations.
Platform: | Size: 1024 | Author: 甲天下 | Hits:

[ARM-PowerPC-ColdFire-MIPS] ALU

Description: ALU可以实现16种操作（包括加减乘除移位运算等）-ALU can be 16 kinds of operations (including addition and subtraction multiplication and division shift operator, etc.)
Platform: | Size: 838656 | Author: 草野彰 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 一个桶形移位寄存器的.v文件，含testbench-Shift Registers a bucket. V file containing Testbench
Platform: | Size: 1024 | Author: QU YIFAN | Hits:

[VHDL-FPGA-Verilog] LFSR

Description: 自动生成线形反馈移位寄存器的各种HDL源代码和原理图的工具-Automatic generation of linear feedback shift register of a variety of HDL source code and schematic tools
Platform: | Size: 162816 | Author: zx | Hits:

[Other Embeded program] ShiftRegister

Description: Shift register verilog code
Platform: | Size: 1024 | Author: selcuk | Hits:

[VHDL-FPGA-Verilog] shift_register

Description: 用Verilog实现的移位寄存器，可以实现左移、右移等功能-Using Verilog implementation of the shift register, you can achieve the left, shifted to right and other functions
Platform: | Size: 3072 | Author: huhahuha | Hits:

[VHDL-FPGA-Verilog] shift_reg

Description: shift register. vhdl verilog
Platform: | Size: 1024 | Author: shezzzz | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 文件包含了寄存器，移位寄存器，可能计数器，计数器等用VHDL实现的功能模块。-File contains the register, shift register, may counter, counter, implemented with the VHDL modules.
Platform: | Size: 4096 | Author: 朱向南 | Hits:

[VHDL-FPGA-Verilog] Shift-register

Description: 两种移位寄存器——通用和桶形移位寄存器，用硬件描述语言Verilog编写，适合初学者。-Two kinds of shift register- common and barrel shift register in Verilog hardware description language, suitable for beginners
Platform: | Size: 2048 | Author: 李菲 | Hits:

[Other] Verilog-shift-mulfunction

Description: FPGA verilog 实现任意位宽的移位相乘法，有符号小数或者有符号整数相乘。函数调用方式-FPGA verilog achieve any bit-wide shift multiplication , signed or signed decimal integer multiplication . Function call
Platform: | Size: 1024 | Author: 李潇 | Hits:

[Other] Verilog-shift-mul

Description: FPGA verilog 实现任意位宽的移位相乘法，有符号小数或者有符号整数相乘非函数调用-FPGA verilog achieve any bit-wide shift multiplication , signed or signed decimal integer multiplication non- function call
Platform: | Size: 2048 | Author: 李潇 | Hits:

[VHDL-FPGA-Verilog] shift-register

Description: FPGA/CPLD 的verilog移位寄存器代码。-verilog shift register code.
Platform: | Size: 1024 | Author: john | Hits:

[assembly language] Verilog源代码

Description: 多种基本功能的Verilog代码实现，包括多路选择器，二进制到BCD码转换，二进制到格雷码转换，7段译码器，8位数据锁存器，移位寄存器等等多种功能。(Verilog code implementation of a variety of basic functions, including multiplexer, binary to BCD code conversion, binary to Gray code conversion, 7-segment decoder, 8-bit data latch, shift register and many other functions.)
Platform: | Size: 18432 | Author: MMK1 | Hits:
« 12 3 4 5 6 7 8 9 10 »

CodeBus www.codebus.net