Search - verilog rtl

[VHDL-FPGA-Verilog] rtl

Description: 用verilog编写的网卡芯片rtl级。前仿后仿都通过了，可以在modelsim上运行察看-verilogrtl After the former imitation through imitation, it can run on the look modelsim
Platform: | Size: 93184 | Author: 刘吉 | Hits:

[VHDL-FPGA-Verilog] rtl

Description: JTAG design verilog code.
Platform: | Size: 4096 | Author: assa | Hits:

[VHDL-FPGA-Verilog] 8051

Description: 8051核Verilog实现源代码，有兴趣的可以看看。-8051 nuclear realize Verilog source code, are interested can look at.
Platform: | Size: 252928 | Author: 偶的 | Hits:

[Speech/Voice recognition/combine] speech

Description: 用verilog HDL实现自相关算法！ RTL级可综合代码！通过modelsim5.6仿真和quartusii7.1综合！-Verilog HDL using auto-correlation algorithm to achieve! RTL-level code can be integrated! Through simulation and modelsim5.6 integrated quartusii7.1!
Platform: | Size: 3072 | Author: ji | Hits:

[SCM] 8051_IP_Verilog

Description: 8051单片机源码verilog版本包括rtl， testbench， synthesis -Verilog source code version of 8051, including rtl, testbench, synthesis
Platform: | Size: 508928 | Author: carol | Hits:

[VHDL-FPGA-Verilog] i2c.tar

Description: 是个I2C软核，使用verilog和vhdl实现的，含有testbench。-this is soft core of I2C in verilog rtl and VHDL.
Platform: | Size: 702464 | Author: 杨力 | Hits:

[VHDL-FPGA-Verilog] RTL

Description:
Platform: | Size: 91136 | Author: Dee | Hits:

[VHDL-FPGA-Verilog] watch_dog_rtl_source

Description: Watchdog timer verilog RTL code
Platform: | Size: 10240 | Author: Chris | Hits:

[VHDL-FPGA-Verilog] timer_rtl_source

Description: Timer verilog RTL code
Platform: | Size: 11264 | Author: Chris | Hits:

[VHDL-FPGA-Verilog] uart_0910

Description: uart串口传输的verilog RTL级源码，已通过仿真验证。文件主要包含发送、接受位处理，发送、接受字节帧处理，对学习串口通信的朋友很有帮助-uart serial transmission verilog RTL-level source code has been verified by simulation. File mainly contains the send, receive digital processing, sending, receiving bytes of frame processing, serial communications, a friend of learning helps
Platform: | Size: 7168 | Author: 李鹏 | Hits:

[VHDL-FPGA-Verilog] async_fifo

Description: verilog HDL写的异步fifo代码及测试平台，直接可用，可生成RTL代码-asynchronous fifo write verilog HDL code and test platform, directly available, can generate RTL code for
Platform: | Size: 62464 | Author: 张晗 | Hits:

[Other] rtl

Description: ddr controller in verilog-ddr controller in verilog...............
Platform: | Size: 69632 | Author: guanchuanjian | Hits:

[VHDL-FPGA-Verilog] 8bit_RISC_CPU_RTL_Code

Description: 8位RISC CPU 内核源码(VERILOG版)-8 bit RSIC CPU RTL code(Verilog)
Platform: | Size: 79872 | Author: 曾亮 | Hits:

[Other] rtl

Description: SPI verilog RTL code
Platform: | Size: 5120 | Author: china | Hits:

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[VHDL-FPGA-Verilog] rtl

[VHDL-FPGA-Verilog] rtl

[VHDL-FPGA-Verilog] 8051

[Speech/Voice recognition/combine] speech

[SCM] 8051_IP_Verilog

[VHDL-FPGA-Verilog] i2c.tar

[VHDL-FPGA-Verilog] RTL

[VHDL-FPGA-Verilog] watch_dog_rtl_source

[VHDL-FPGA-Verilog] timer_rtl_source

[VHDL-FPGA-Verilog] uart_0910

[VHDL-FPGA-Verilog] async_fifo

[Other] rtl

[VHDL-FPGA-Verilog] 8bit_RISC_CPU_RTL_Code

[Other] rtl

[Compress-Decompress algrithms] intra(verilog)

[VHDL-FPGA-Verilog] USB2.0IP(RTL)

[VHDL-FPGA-Verilog] IFFT-RTL

[VHDL-FPGA-Verilog] i2c

[VHDL-FPGA-Verilog] mdio

[VHDL-FPGA-Verilog] IEEE-Std-1364.1-2002-Verilog-RTL-Synthesys

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