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[Algorithm] U-rand(0-100)

Description: 0-100伪随机数发生函数代码，希望程序能用得上，-0-100 pseudo-random number generating function codes, procedures can hope that none?
Platform: | Size: 1024 | Author: 陈波 | Hits:

[Books] Hardware_Description_Language_Verilog(Version4).ra

Description: 中文名称为：硬件描述语言 Verilog（第四版）。讲解verilog HDL的经典图书。Thomas和Moorby编著，内容涵盖了:行为建模、并发进程、逻辑级建模、高级时序、逻辑综合、行为综合等方面的内容。通读此书后，不需要再读其他的verilog书籍。-Chinese name is: Hardware Description Language Verilog (Fourth Edition). Verilog HDL on classic books. Thomas and Moorby authoring, content covers: behavioral modeling, concurrent process, logic-level modeling, advanced timing, logic synthesis, behavior and other aspects of integrated content. After reading this book, do not need to read other books of Verilog.
Platform: | Size: 5331968 | Author: 王敏 | Hits:

[VHDL-FPGA-Verilog] a_block_with_several_functions_with_Verilog_HDL.ra

Description: Verilog是广泛应用的硬件描述语言，可以用在硬件设计流程的建模、综合和模拟等多个阶段。随着硬件设计规模的不断扩大，应用硬件描述语言进行描述的CPLD结构，成为设计专用集成电路和其他集成电路的主流。通过应用Verilog HDL对多功能电子钟的设计，达到对Verilog HDL的理解，同时对CPLD器件进行简要了解。 本文的研究内容包括: 对Altera公司Flex 10K系列的EPF10K 10简要介绍，Altera公司软件Max+plusⅡ简要介绍和应用Verilog HDL对多功能电子钟进行设计。 -Verilog is the most widely used hardware description language.It can be used to the modeling, synthesis, and simulation stages of the hardware system design flow. With the scale of hardware design continually enlarging, describing the CPLD with HDL become the mainstream of designing ASIC and other IC.To comprehend Verilog HDL and get some knowledge of CPLD device, we design a block with several functions with Verilog HDL. This thesis is about to discuss the above there aspects: Introduce the EPF10K 10 of Flex 10K series producted by Altera Corporation simply. the software Max+plusⅡ,Design the block with several functions with Verilog HDL.
Platform: | Size: 482304 | Author: li | Hits:

[Program doc] Performance_Comparisons_between_FLL_PLL_and_DLL.ra

Description:
Platform: | Size: 108544 | Author: xinmuwang | Hits:

[VHDL-FPGA-Verilog] RA

Description: ripple adder 程式撰寫,此利用verilog撰寫-ripple adder
Platform: | Size: 2048 | Author: 鍾潤宏 | Hits:

[VHDL-FPGA-Verilog] Digital_System_Design_with_SystemVerilog(draft).ra

Description: This book is intended as a student textbook for both undergraduate and postgraduate students.-This book is intended as a student textbook for both undergraduate and postgraduate students. The majority of Verilog and SystemVerilog books are aimed at practicing engineers. Therefore, some features of SystemVerilog are not described at all in this book. Equally, aspects of digital design are covered that would not be included in a typical SystemVerilog book.
Platform: | Size: 1875968 | Author: jiaquan | Hits:

[Software Engineering] A-Verilog-Model-of-Universal-Sequence-Detector.ra

Description: a verilog model of universal seq detector
Platform: | Size: 159744 | Author: Sasanka | Hits:

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