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[VHDL-FPGA-Verilog] miniMIPS

Description: 这是一个基于mips-I结构的处理器,32bit,冯诺依曼结构-This is based on a MIPS- I structure of the processor, 32bit, von Neumann structure
Platform: | Size: 222208 | Author: tsm998 | Hits:

[Other] arm7-verilog

Description: 这是arm7处理器的verilog全代码，仔细研究一下，会对CPU和verilog均有很大的裨益。-This is ARM7 processor Verilog-wide code carefully, CPU and Verilog will have great benefits.
Platform: | Size: 37888 | Author: 王云 | Hits:

[MPI] controller

Description: MIPS处理器的控制verilog代码，可综合，可仿真，属硬件描述语言，集成电路设计代码-MIPS control processor Verilog code can be integrated to simulation, a hardware description language, integrated circuit design code
Platform: | Size: 1024 | Author: 陈丰 | Hits:

[Other] ask10

Description: This a simple MIPS processor datapath written in VERILOG hardware language. You can see the signals when emulating in signalscan. Compile it with verilog in linux.-This is a simple MIPS processor datapath written in VERILOG hardware language. You can see the signals when emulating in signalscan. Compile it with verilog in linux.
Platform: | Size: 2048 | Author: thesky | Hits:

[ARM-PowerPC-ColdFire-MIPS] mips_multi

Description: mips processor multicycle non-pipelined microprocessor by verilog
Platform: | Size: 9216 | Author: JACD | Hits:

[VHDL-FPGA-Verilog] mips

Description: 使用verilog設計的MIPS處理器，mips處理機的模擬且可合成驗証-MIPS processor using the verilog design, mips processor synthesis of analog and can be verified
Platform: | Size: 4096 | Author: 張日 | Hits:

[VHDL-FPGA-Verilog] mlite.tar

Description: 很强大的mips处理器，用verilog实现的-A very strong mips processor implemented using verilog
Platform: | Size: 129024 | Author: 李仓 | Hits:

[VHDL-FPGA-Verilog] m1_core.tar

Description: 一个小巧的mips处理器，verilog写的，大家可以-A small mips processor, verilog written, we can see
Platform: | Size: 21504 | Author: 李仓 | Hits:

[Other] mips789.tar

Description: 一个功能很完善，很强大的mips处理器，verilog编写的-A feature is perfect, very strong mips processor, verilog prepared
Platform: | Size: 3522560 | Author: 李仓 | Hits:

[assembly language] hmc-mips-7-3-15

Description: mips processor in verilog
Platform: | Size: 1691648 | Author: henry | Hits:

[VHDL-FPGA-Verilog] mips

Description: in verilog 8bit mips processor
Platform: | Size: 2751488 | Author: Lee Jonggun | Hits:

[VHDL-FPGA-Verilog] MIPS_Project

Description: Verilog Source File. MIPS Processor Pipelining
Platform: | Size: 4147200 | Author: JihwanKim | Hits:

[VHDL-FPGA-Verilog] multi_cycle_Verilog

Description: this code has written in verilog and it is about multi cycle mips processor .This code can do alot of jobs for examole,add ,addi ,addiu,and ,andi,ori ,mfhi.mfho,xor,slt,slti,ssw,lw,lui ,jal ,mult ,multu,... and it can multiply two input inter less than 32 bits in 32 clocks .
Platform: | Size: 4096 | Author: sajad | Hits:

[VHDL-FPGA-Verilog] MIPS-processor-Verilog-code

Description: 原创，MIPS处理器Verilog源码，在FPGA实现单周期MIPS处理器，实现存储访问指令load word(lw)和store word(sw)，算术逻辑指令add、addi、sub、and、or和slt跳转指令branch equal(beq)和jump(j)-Original, achieves single-cycle MIPS processor MIPS processor Verilog source code, the FPGA, storage access instructions load word (lw) and store word (sw) arithmetic logic instructions add, addi, sub, and, or, and slt jump instructionbranch equal (beq, which) and jump (j)
Platform: | Size: 7168 | Author: ZLS | Hits:

[VHDL-FPGA-Verilog] MIPS-multi-cycle-(Quarters-II--Verillig)

Description: Multi cycle MIPS processor verilog
Platform: | Size: 2225152 | Author: zzang1323 | Hits:

[ARM-PowerPC-ColdFire-MIPS] Verilog-Source

Description: mips 处理器verilog文件， 适合做处理器开发的人员参考-the mips processor verilog file suitable processor development reference
Platform: | Size: 24576 | Author: nx74110 | Hits:

[VHDL-FPGA-Verilog] s_mips

Description: FPGA verilog mips processor - pipeline reference
Platform: | Size: 2048 | Author: howyaaa | Hits:

[Other] MIPS

Description: MIPs Processor in Verilog
Platform: | Size: 3533824 | Author: Ferney | Hits:

[VHDL-FPGA-Verilog] MIPS

Description: 用verilog编写的简单的类MIPS多周期流水化处理器实现，基本功能包括9条指令和两位动态分支预测，压缩包里的word详细说明了结构中的细节-Written by verilog simple class multi-cycle pipelined MIPS processor, the basic features include 9 instruction and two dynamic branch prediction, compressed bag word specifies the details of the structure
Platform: | Size: 239616 | Author: csy | Hits:

[VHDL-FPGA-Verilog] 北航MIPS多周期

Description: 多周期流水线处理器的verilog实现。(The Verilog implementation of a multi cycle pipelined processor.)
Platform: | Size: 14572544 | Author: jetyeah | Hits:
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