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[
VHDL-FPGA-Verilog
]
taxi1
Description:
出租车计价器，简单、方便，采用verilog hdl语言编写，所用平台是MAXPLUS软件-Taximeter, simple, convenient, using Verilog HDL language, by using the platform of software Segments
Platform:
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Size:
976896
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Author:
zhz
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Search - verilog hdl Maxpl