Description: 这是我用verilog hdl语言写的浮点乘法器,用的是基4的booth算法,对于部分积使用了5-2压缩和3-2压缩,欢迎大家指点,也欢迎大家把它改成流水线以提高速度.-This is my verilog hdl language used to write floating-point multiplier, using a Radix-4 algorithm for the booth for part of the plot using the 5-2 and 3-2 compression compression, welcomed everyone pointing, also welcomed the U.S. put it into a pipeline to improve speed. Platform: |
Size: 4096 |
Author:lanty |
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Description: 实现4位乘法器的流水线操作计算，便于理解流水线(The implementation of pipelined operation of 4 bit multiplier is convenient for understanding pipelining) Platform: |
Size: 105472 |
Author:yuanjingwei
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