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[VHDL-FPGA-Verilog] XC9536XL

Description: 通用FPGA CPLD下载电缆的XC9536XL编译程序-Universal FPGA CPLD download cable XC9536XL compiler
Platform: | Size: 4096 | Author: | Hits:

[VHDL-FPGA-Verilog] alu

Description: 设计带进位算术逻辑运算单元，根据74LS181功能表，用Verilog HDL硬件描述语言编程实现ALU181的算术逻辑运算功能，编辑实验原理图，在算术逻辑单元原理图上，将其扩展为带进位的算术逻辑运算单元，对其进行编译，并设计波形对其进行仿真验证，最后下载验证-Design into the digital arithmetic logic operation unit, in accordance with menu 74LS181 with Verilog HDL hardware description language programming ALU181 function arithmetic logic operations, editing Experimental schematic diagram, in the Arithmetic Logic Unit schematic diagram on its expansion into the spaces for arithmetic logic operation unit, its compiler, and the design of their simulation waveforms, and finally download the verification
Platform: | Size: 667648 | Author: 623902748 | Hits:

[VHDL-FPGA-Verilog] LogicAnalysisOneMod

Description: 建议逻辑分析仪输出驱动程序，quartus II编译通过，内含TLC7528的Verilog HDL驱动，下载测试通过-Proposed logic analyzer output driver, quartus II compiler is passed, the Verilog HDL containing TLC7528 driver, download the test
Platform: | Size: 907264 | Author: huyanchao | Hits:

[VHDL-FPGA-Verilog] VGA_test50m

Description: 本代码功能为实现VGA显示功能，即实现在显示器上显示640*480彩条。 程序通过quartusII 8.1编译，使用verilog语言编写。 可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。 （开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm） 有需要的朋友可以下载参考-The code functions to achieve the VGA display, that is, to achieve the display 640* 480 Color display. Procedure quartusII 8.1 compiler, use the verilog language. Bin Jie in science and technology* BJTECH company' s development board based on altera epm240 verification. (Development Board web site http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm) in need of friends can download reference
Platform: | Size: 47104 | Author: 彬杰科技 | Hits:

[VHDL-FPGA-Verilog] IR

Description: 本代码功能为实现38/30KHZ红外线接收功能 程序通过quartusII 8.1编译，使用verilog语言编写。 可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。 （开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm） 有需要的朋友可以下载参考-The code functions to achieve 38/30KHZ infrared reception procedure quartusII 8.1 compiler, use the verilog language. Bin Jie in science and technology* BJTECH company' s development board based on altera epm240 verification. (Development Board web site http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm) in need of friends can download reference
Platform: | Size: 78848 | Author: 彬杰科技 | Hits:

[VHDL-FPGA-Verilog] ps2test

Description: 本代码功能为实现接收PS2键盘编码功能。 程序通过quartusII 8.1编译，使用verilog语言编写。 可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。 （开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm） 有需要的朋友可以下载参考-The code functions to achieve the receiver PS2 keyboard encoding. Procedure quartusII 8.1 compiler, use the verilog language. Bin Jie in science and technology* BJTECH company' s development board based on altera epm240 verification. (Development Board web site http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm) in need of friends can download reference
Platform: | Size: 118784 | Author: 彬杰科技 | Hits:

[VHDL-FPGA-Verilog] recuart_50m

Description: 本代码功能为实现接收PC发送的串口数据功能 程序通过quartusII 8.1编译，使用verilog语言编写。 可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。 （开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm） 有需要的朋友可以下载参考-The code functions to achieve the receiving PC to send serial data capabilities procedure quartusII 8.1 compiler, use the verilog language. Bin Jie in science and technology* BJTECH company' s development board based on altera epm240 verification. (Development Board web site http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm) in need of friends can download reference
Platform: | Size: 48128 | Author: huangbin | Hits:

[VHDL-FPGA-Verilog] halfclk

Description: 本代码功能为实现输入时钟的1.5分频功能。 程序通过quartusII 8.1编译，使用verilog语言编写。 可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。 （开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm） 有需要的朋友可以下载参考-The code functions as the input clock frequency of 1.5 features. Procedure quartusII 8.1 compiler, use the verilog language. Bin Jie in science and technology* BJTECH company' s development board based on altera epm240 verification. (Development Board web site http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm) in need of friends can download reference
Platform: | Size: 28672 | Author: huangbin | Hits:

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