Description: 编写verilog代码
利用实验箱上的A/D芯片完成模数转换。输入电压由实验箱提供,其幅值在0~5V间变化,由电位器控制。输出信号显示输入的模拟电压值,由数码管显示为2位BCD码的形式。-The preparation of Verilog code box on the use of experimental A/D chip to complete analog-digital conversion. Input voltage provided by the experimental box, and its amplitude in the 0 ~ 5V between changes in control by potentiometer. Output signal shows that the value of analog voltage input from a digital display for two BCD code of the form. Platform: |
Size: 22528 |
Author:Ericwhu |
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Description: it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit. -it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit. Platform: |
Size: 6144 |
Author:yasir ateeq |
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Description: Altera公司推出最新开发板DE1。该资料为DE1的FPGA 代码,包括ADC,音频处理,视频输出等,供大家参考使用。-Altera Corporation introduced the latest development board DE1. The data for the DE1 FPGA code, including the ADC, audio processing, video output, etc., for your use and reference. Platform: |
Size: 11901952 |
Author:小陈 |
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Description: ADI JESD204接口的ADC与Xilinx FPGA接口IP,包含Verilog和VHDL源代码,AXI总线接口,ADC串行控制接口-ADI IP for interfacing JESD204 ADC to Xilinx FPGA, include Verilog/VHDL source code, AXI interface and serial config interface
Platform: |
Size: 77824 |
Author:Eddie |
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