Search - verilog c

[Embeded-SCM Develop] 148个verilog hdl小程序（有很多testbench）——

Description: 148个verilog hdl小程序（有很多testbench）——.-148 Verilog HDL small programs (many testbench) from Part
Platform: | Size: 55296 | Author: 地方 | Hits:

[VHDL-FPGA-Verilog] 9.16fifoasi

Description: 主要完成数字电视前端信号处理和缓冲作用的verilog源代码，可以直接使用 -the major digital TV front-end signal processing and buffer the Verilog source code can be used directly
Platform: | Size: 2761728 | Author: yjb_21cn | Hits:

[VHDL-FPGA-Verilog] Computer Architecture Handbook on Verilog HDL

Description: Computer Architecture Handbook on Verilog HDL
Platform: | Size: 66560 | Author: 路路 | Hits:

[VHDL-FPGA-Verilog] 数据结构c描述习题集答案

Description: 减1计数器一、设计要求用Verilog HDL语言设计一个计数器。要求计数器具有异步置位/复位功能，可以进行自增和自减计数，其计数周期为2^N（N为二进制位数）。二、设计原理输入/输出说明： d：异步置数数据输入； q：当前计数器数据输出； clock：时钟脉冲； count_en：计数器计数使能控制（1：计数/0：停止计数）； updown：计数器进行自加/自减运算控制（1：自加/0：自减）； load_d-a counter a reduction, design requirements using Verilog HDL design of a counter. Asynchronous requests with counter-home/reset functions can be carried out by self and self-count reduction, cycle counting of 2 ^ N (N for binary digit). Second, the principle of design input/output Description : d : asynchronous home several data input; Q : The current counter data output; Clock : clock pulse; Count_en : Counting enable control (1 : Counting/0 : Stop counting); Updown : dollars several self-Canada/reduction Operational control (1 : Since the plus/0 : Since decrease); load_d
Platform: | Size: 111616 | Author: tutu | Hits:

[SCM] STC89C51RCRD+系列内部 EEPROM 放数据(C语言) _c

Description: STC89C51RCRD+系列内部 EEPROM存放数据(C语言)，此款单片机可是物美价廉啊！！！ -STC89C51RCRD series of internal EEPROM data storage (C language) says the Catholic SCM But ah! ! !
Platform: | Size: 5120 | Author: 经济学 | Hits:

[Audio program] WM8731

Description: 高品质音频编解码器WM8731的Verilog使用程序。-high-quality audio codec WM8731 Verilog procedures.
Platform: | Size: 7168 | Author: 李全 | Hits:

[Other] ImplementationFromAlgorithmDesigntoHardwareLogic.r

Description: 第一章数字信号处理、计算、程序、算法和硬线逻辑的基本概念第二章 Verilog HDL设计方法概述第三章 Verilog HDL的基本语法第四章不同抽象级别的Verilog HDL模型第五章基本运算逻辑和它们的Verilog HDL模型第六章运算和数据流动控制逻辑-the first chapter of digital signal processing and computing procedures, hard-line algorithm and the basic logic of the concept of the second chapter of Verilog HDL design methods outlined in the third chapter Verilo g HDL basic grammar Chapter 4 different levels of abstract Verilog HDL model V basic arithmetic logic and their Verilog HDL model of the sixth chapter operations and data flow control logic
Platform: | Size: 421888 | Author: 陈亨利 | Hits:

[Editor] verilog_source_insight_clf

Description: SOURCE INSIGHT的verilog语法插件，SOURCE INSIGHT支持自动完成等功能，是一个不错的硬件语言编辑分析器-SOURCE INSIGHT verilog syntax of plug-ins, SOURCE INSIGHT done automatically, and other support functions, is a good language editing hardware analyzers
Platform: | Size: 3072 | Author: 洪炉 | Hits:

[ARM-PowerPC-ColdFire-MIPS] arm7_core_verilog

Description: arm7timi架构的verilog代码，可以仿真，通过学习，可以掌握arm7内部架构。-arm7timi verilog structure of the code can be simulated, through learning, be able arm7 internal structure.
Platform: | Size: 677888 | Author: blueli | Hits:

[VHDL-FPGA-Verilog] mipsinverilogandvhdl

Description: mips prcessor in Verilog and vhdl-mips prcessor in vhdl and Verilog
Platform: | Size: 7168 | Author: 张六封 | Hits:

[SCM] DDS+51

Description: 本程序功能: DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,"C"文件夹内,是用于在 51 单片机上运行的 C语言程序, "Verilog"文件夹内,是用Verilog语言编写的 FPGA 程序.-this program functions : DDS folder procedures, complete direct digital frequency synthesis, sine, triangle, Three square waveform, and can sweep. can be set up through the keyboard operation frequency waveform parameters and the types of choice and control operations. composed of two parts, "C" folder, for the 51 microcontroller running C Programming Language, "Verilog" folder, use the Verilog language FPGA procedures.
Platform: | Size: 1027072 | Author: 吴健 | Hits:

[VHDL-FPGA-Verilog] dct

Description: 里面含有vhdl和verilog 版本,很好用!dct变换用得很多啊!-Which contains a VHDL and Verilog versions of very good use! Dct transform with a lot ah!
Platform: | Size: 124928 | Author: 萧勇 | Hits:

[2D Graphic] jpeg_v

Description: JPEG的Verilog源代码，很有参考价值-JPEG of the Verilog source code, useful reference
Platform: | Size: 222208 | Author: 张伟 | Hits:

[Algorithm] fft-C

Description: 采用C语言设计的FFT代码，在C语言下调试通过。文件为word文档，需要嵌入到自己的程序中-Using C language designed FFT code in C language under the debugger through. Document for the word document, the need to embed into their own procedures
Platform: | Size: 3072 | Author: 李文良 | Hits:

[Other Embeded program] dds_drive.c

Description: DDS发生器NIOS .c文件,在NIOSII中可以配合Verilog代码生成的自定义外设产生DDS信号-DDS generator NIOS. C files, NIOSII can be in Verilog code generation with custom peripherals DDS generated signal
Platform: | Size: 4096 | Author: 白天 | Hits:

[VC/MFC] HandelC

Description: Handel-C语言的学习文档。Handel-C语言由C/C++演化而来，可以自动实现C到VHDL、C到Verilog、C到EDIF等转换。在DK环境中，DK+Handel-C工具能直接把基于C语言的设计转变为优化的HDL(可以实现：C到VHDL、C到Verilog、C到EDIF等的自动生成)，进而通过FPGA实现，从而保证了各种复杂的高难算法在工程应用的实时性。-Handel-C language documentation. Handel-C language by C/C++ Evolved, you can automatically C to VHDL, C to Verilog, C, etc. to convert Edif. In DK environment, DK+ Handel-C tools can be directly to the C language-based design into optimized HDL (can be achieved: C to VHDL, C to Verilog, C, etc. to Edif automatically generated), then through the FPGA to achieve, thus ensuring a variety of complex algorithms in difficult real-time engineering applications.
Platform: | Size: 1439744 | Author: 杜杰 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: Verilog HDL是一种硬件描述语言，用于从算法级、门级到开关级的多种抽象设计层次的数字系统建模。被建模的数字系统对象的复杂性可以介于简单的门和完整的电子数字系统之间。数字系统能够按层次描述，并可在相同描述中显式地进行时序建模。　　Verilog HDL 语言具有下述描述能力：设计的行为特性、设计的数据流特性、设计的结构组成以及包含响应监控和设计验证方面的时延和波形产生机制。所有这些都使用同一种建模语言。此外，Verilog HDL语言提供了编程语言接口，通过该接口可以在模拟、验证期间从设计外部访问设计，包括模拟的具体控制和运行。 -Verilog HDL语言不仅定义了语法，而且对每个语法结构都定义了清晰的模拟、仿真语义。因此，用这种语言编写的模型能够使用Verilog仿真器进行验证。语言从C编程语言中继承了多种操作符和结构。Verilog HDL提供了扩展的建模能力，其中许多扩展最初很难理解。但是，Verilog HDL语言的核心子集非常易于学习和使用，这对大多数建模应用来说已经足够。当然,完整的硬件描述语
Platform: | Size: 32106496 | Author: 杨恩源 | Hits:

[ELanguage] MIP-C

Description: mips-c指令系统,用Verilog实现-mips-c command systems, using Verilog realization of
Platform: | Size: 1310720 | Author: 文化 | Hits:

[VHDL-FPGA-Verilog] CPU

Description: verilog编写CPU： 1. 哈佛存储器结构，大端格式； 2. 类MIPS精简指令集，支持子程序调用和软中断； 3. 实现了乘除法； 4. 五级流水线，工作频率可达80MHz（每个时钟周期一条指令，不计流水线冲突）。 -MIPS like CPU using verilog
Platform: | Size: 17408 | Author: yk | Hits:

[VHDL-FPGA-Verilog] I2C_code

Description: 与IP核配套的I2C-Master Core，包含了目前主流FPGA芯片的I2C实现，代码包括Altera/Xilinx/OpenCore等公司的VHDL/Verilog/C等。-I2C-Master Core
Platform: | Size: 3256320 | Author: summerooooo | Hits:

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