Search - verilog TxD

[VHDL-FPGA-Verilog] tx

Description: 自己编写的串口UART发送的Verilog模块。与FIFO连接，可以实现自动连续发送。-I have written serial UART to send the Verilog module. Connect with the FIFO, you can realize automatic continuous send.
Platform: | Size: 7168 | Author: YongZhiLi | Hits:

[Com Port] UART_TXD_RXD_Verilog

Description: 开发异步串口FPGA逻辑的说明文档及代码，其中代码用Verilog编写，我就是看这些文档和源码编写了自己的串口程序-uart,txd,rxd ,select baud
Platform: | Size: 337920 | Author: tony | Hits:

[VHDL-FPGA-Verilog] txd

Description: 用verilog实现的串口发送程序，和之前的发送程序可以一起使用，仿真通过-Verilog achieve serial transmission program, and before sending program can be used in conjunction with simulation through
Platform: | Size: 309248 | Author: hr | Hits:

[VHDL-FPGA-Verilog] txd_control

Description: uart串口发送控制模块适合于485 422 232等接口-uart TXD——contrl Verilog
Platform: | Size: 1024 | Author: 王长友 | Hits:

[VHDL-FPGA-Verilog] project2

Description: 基于Verilog在quartus平台上搭建的串口通信模型，适用于初学者。本实验所用RXD的波特率为9600，TXD波特率为9600×16，1位起始位，8位数据位（ASCII码），1位停止位，无奇偶校检位。接收数据时，至少连续采样8个周期都是“0”后，才认定为起始位，之后每隔16个周期取一次数据。(Verilog based on the quartus platform to build a serial communication model, suitable for beginners.)
Platform: | Size: 116736 | Author: 锂离子 | Hits:

[VHDL-FPGA-Verilog] txd_interface

Description: 串口发送接口控制联合uart_txd_contrl实现(uart TXD Verilog)
Platform: | Size: 1024 | Author: 王峰 | Hits:

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