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[VHDL-FPGA-Verilog] CAN_IP

Description: 这是CAN总线控制器的IP核，源码是由Verilog HDL编写的。其硬件结构与SJA1000类似，满足CAN2.0B协议。-This is a IP core of the CAN bus controller written by the Verilog HDL. whose structure is similar with SJA1000,supporting the protocol of CAN2.0B.
Platform: | Size: 61440 | Author: 普林斯 | Hits:

[VHDL-FPGA-Verilog] CAN--for-FPGA

Description: FPGA控制SJA1000实现CAN协议 适合深入学子FPGA的学生 很不错-FPGA control the SJA1000 CAN protocol for in-depth realization of the students are very good students FPGA
Platform: | Size: 17577984 | Author: qzl001 | Hits:

[Other] can_acf

Description: can ctrl sja1000 compatible written in verilog part of the files
Platform: | Size: 3072 | Author: pecce | Hits:

[Other] hdl

Description: can ctrl sja1000 compatible written in verilog part of the files
Platform: | Size: 46080 | Author: pecce | Hits:

[VHDL-FPGA-Verilog] CAN

Description: 包含CAN协议讲解与CAN协议控制器的verilog实现(含有testbench），该实现模仿SJA1000架构，接口完全一致。压缩包中还包含SJA1000的手册与应用指南，非常好的CAN学习资料。-CAN protocol controller implemented in Verilog（contain testbench） & instruction of CAN protocol & datasheet and user manual of SJA1000
Platform: | Size: 12809216 | Author: zhangsong | Hits:

[SCM] sja1000datasheet_and_c_CODE

Description: SJA1000芯片中文资料和单片机C程序代码，可辅助完成Verilog程序编写，很实用-SJA1000 chip Chinese data and microcontroller C program code, can help complete the preparation of the Verilog program, very practical
Platform: | Size: 1226752 | Author: hanfeng | Hits:

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