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Search - verilog 8 bit comparator - List
[
VHDL-FPGA-Verilog
]
8位大小比较器
DL : 0
8位大小比较器的VHDL源代码,Magnitude Comparator VHDL description of a 4-bit magnitude comparator with expansion inputs-eight compared with the size of the VHDL source code, Magnitude Comparator VHDL description of a 4-bit magnitude comparator inputs with expansion
Date
: 2025-07-04
Size
: 1kb
User
:
蔡孟颖
[
VHDL-FPGA-Verilog
]
8bit_cample
DL : 0
这是用数据流来设计的8位比较器,很简单,也很使用,希望能有所帮助,谢谢批评指导-This is used to design data stream 8-bit comparators, is simple and the use of, hoping to be helpful, thank you criticize guidance
Date
: 2025-07-04
Size
: 2kb
User
:
赵正鑫
[
VHDL-FPGA-Verilog
]
comparator
DL : 0
8位二进制的数值比较器,这是用verilog hdl语言中的行为建模写的-8-bit binary value of the comparator, which is used in the verilog hdl behavioral modeling language to write
Date
: 2025-07-04
Size
: 144kb
User
:
黄启
[
ARM-PowerPC-ColdFire-MIPS
]
vivado
DL : 0
用中规模MSI基本逻辑功能模块 实现关模比较器(要求分别使用中规模和语言实现): 功能要求:它的输入是两个8位无符号二进制整数X和Y,以及一个控制信号S;输出信号为1个8位无符号二进制整数Z。输入输出关系为:当S=1时, Z=min(X,Y);当S=0时, Z=max(X,Y)。(Modeling comparator is implemented by using basic logic function modules of medium-scale MSI (medium-scale and language are required respectively): Functional requirements: Its input is two 8-bit unsigned binary integers X and Y, and a control signal S; the output signal is an 8-bit unsigned binary integer Z. The relationship between input and output is: when S = 1, Z = min (X, Y); when S = 0, Z = max (X, Y).)
Date
: 2025-07-04
Size
: 10kb
User
:
瘾1581
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