Search - veilog

[Other resource] and_or

Description: veilog 代码用户可以直接调用，作为底层模块。同时已经编译成功，可以作为基本单元库。-veilog code user can derict use it for the base mode.
Platform: | Size: 3531 | Author: 宋昆仑 | Hits:

[Other] statemachine_mult

Description: veilog实现的状态机乘法器.可以参考-veilog achieve the state machine multiplier. Can reference
Platform: | Size: 436406 | Author: 陶玉辉 | Hits:

[Other resource] serial_communication

Description: 串口操作源代码，本代码采用veilog hdl语言编写，并经过本人多次验证。-source code, the code used veilog HDL language, and after I repeatedly verified.
Platform: | Size: 3534 | Author: 徐燕玲 | Hits:

Description: 用veilog HDL编的七段译码显示电路。自己做的第一个此类程序，编译仿真通过，感觉不错-veilog HDL series with paragraph 107 of the decoder show circuit. I have done the first such procedure, compile through simulation, feeling good
Platform: | Size: 2059 | Author: 孙忠诚 | Hits:

[Other resource] count_usebasketball

Description: 一个小程序，用Veilog HDL编写的，可以用于篮球比赛的倒计时牌，已在max-plusII上仿真通过。-a small program, prepared by the Veilog HDL, can be used for the basketball game countdown. have max-plusII on through simulation.
Platform: | Size: 2202 | Author: 孙忠诚 | Hits:

[Other resource] Verilog_Coding_for_Logic_Synthesis

Description: veilog例程书籍，有8255的例程，还有其他的程序-veilog routines books, 8,255 of routines, there are other procedures
Platform: | Size: 966761 | Author: 刘辉 | Hits:

[Other resource] 24bitdisplay

Description: 一个VEILOG HDL程序，可以直接应用，
Platform: | Size: 104308 | Author: 张金辉 | Hits:

[Program doc] veilog HDL编码规范

Description: 详细介绍了verilog HDL编码的注意事项和基本规范。分为可综合部分，仿真专用部分以及nc-verilog仿真环境的建立。
Platform: | Size: 745126 | Author: venturezhao@gmail.com | Hits:

[VHDL-FPGA-Verilog] and_or

Description: veilog 代码用户可以直接调用，作为底层模块。同时已经编译成功，可以作为基本单元库。-veilog code user can derict use it for the base mode.
Platform: | Size: 3072 | Author: 宋昆仑 | Hits:

[Other] statemachine_mult

Description: veilog实现的状态机乘法器.可以参考-veilog achieve the state machine multiplier. Can reference
Platform: | Size: 436224 | Author: 陶玉辉 | Hits:

[VHDL-FPGA-Verilog] serial_communication

Description: 串口操作源代码，本代码采用veilog hdl语言编写，并经过本人多次验证。-source code, the code used veilog HDL language, and after I repeatedly verified.
Platform: | Size: 3072 | Author: 徐燕玲 | Hits:

[VHDL-FPGA-Verilog] led_decode

Description: 用veilog HDL编的七段译码显示电路。自己做的第一个此类程序，编译仿真通过，感觉不错-veilog HDL series with paragraph 107 of the decoder show circuit. I have done the first such procedure, compile through simulation, feeling good
Platform: | Size: 2048 | Author: 孙忠诚 | Hits:

[VHDL-FPGA-Verilog] count_usebasketball

Description: 一个小程序，用Veilog HDL编写的，可以用于篮球比赛的倒计时牌，已在max-plusII上仿真通过。-a small program, prepared by the Veilog HDL, can be used for the basketball game countdown. have max-plusII on through simulation.
Platform: | Size: 2048 | Author: 孙忠诚 | Hits:

[Other] Verilog_Coding_for_Logic_Synthesis

Description: veilog例程书籍，有8255的例程，还有其他的程序-veilog routines books, 8,255 of routines, there are other procedures
Platform: | Size: 966656 | Author: 刘辉 | Hits:

[VHDL-FPGA-Verilog] VERILOGCOMP

Description:
Platform: | Size: 7168 | Author: 周正华 | Hits:

[VHDL-FPGA-Verilog] 24bitdisplay

Description: 一个VEILOG HDL程序，可以直接应用，-A VEILOG HDL procedures, can be applied directly,
Platform: | Size: 104448 | Author: 张金辉 | Hits:

[VHDL-FPGA-Verilog] PWM

Description:
Platform: | Size: 433152 | Author: 黄朝谦 | Hits:

[VHDL-FPGA-Verilog] spi_verilog

Description: SPI protocol using veilog HDL
Platform: | Size: 6144 | Author: kang | Hits:

[VHDL-FPGA-Verilog] verilog_divdier

Description: veilog中的常用分频器，包括2分频 4分频 8分频等开发环境为ise8.2-veilog commonly used in the dividers, including the 2 frequency divided by 4 divided by 8, such as development environment for ise8.2
Platform: | Size: 2048 | Author: lijin | Hits:

[VHDL-FPGA-Verilog] led_2_0816

Description: veilog程序实现在fpga上流水灯循环显示(Veilog program to achieve in fpga water lamp cycle display)
Platform: | Size: 669696 | Author: wuyezhiyue | Hits:

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[Other resource] and_or

[Other] statemachine_mult

[Other resource] serial_communication

[Other resource] led_decode

[Other resource] count_usebasketball

[Other resource] Verilog_Coding_for_Logic_Synthesis

[Other resource] 24bitdisplay

[Program doc] veilog HDL编码规范

[VHDL-FPGA-Verilog] and_or

[Other] statemachine_mult

[VHDL-FPGA-Verilog] serial_communication

[VHDL-FPGA-Verilog] led_decode

[VHDL-FPGA-Verilog] count_usebasketball

[Other] Verilog_Coding_for_Logic_Synthesis

[VHDL-FPGA-Verilog] VERILOGCOMP

[VHDL-FPGA-Verilog] 24bitdisplay

[VHDL-FPGA-Verilog] PWM

[VHDL-FPGA-Verilog] spi_verilog

[VHDL-FPGA-Verilog] verilog_divdier

[VHDL-FPGA-Verilog] led_2_0816

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