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[VHDL-FPGA-Verilog] uart_verilog

Description: uart串行口,用Verilog编写的.供大家参考-uart serial port, using Verilog prepared. For your reference
Platform: | Size: 10240 | Author: lfy | Hits:

[MPI] Uart_16550_Verilog_Source

Description: UART_16550_verilogHDL源程序，用在lattice芯片上面运行，保证能用的好资料-UART_16550_verilogHDL source, lattice chip used in the above operation can be used to ensure good information
Platform: | Size: 472064 | Author: 成刚 | Hits:

[Other Embeded program] uart

Description: 实现简单的UART功能,在QUARTUS4.0下编译通过,采用VERILOG HDL编写.-Simple UART functions in the compiler under QUARTUS4.0 through using VERILOG HDL preparation.
Platform: | Size: 1024 | Author: 不是 | Hits:

[VHDL-FPGA-Verilog] uart_51

Description: 符合8051协议规范的UART的Verilog源代码.该压缩包是一个modelsim的工程.-8051 agreement in line with the norms of the Verilog source code UART. The Compression Pack is a ModelSim project.
Platform: | Size: 41984 | Author: 王亮 | Hits:

[Com Port] uart

Description: this a Uart source code using Verilog.
Platform: | Size: 10240 | Author: Daniel Zhang | Hits:

[VHDL-FPGA-Verilog] UART

Description: 用FPGA实现了RS232异步串行通信，所用语言是VHDL，另外本人还有Verilog的欢迎交流学习，根据RS232 异步串行通信来的帧格式，在FPGA发送模块中采用的每一帧格式为：1位开始位+8位数据位+1位奇校验位+1位停止位，波特率为2400。由设置的波特率可以算出分频系数，具体算法为分频系数X=CLK/(BOUND*2)。-Using FPGA to achieve the RS232 asynchronous serial communication, the language used is VHDL, In addition, I also welcome the exchange of learning Verilog, according to RS232 asynchronous serial communication to the frame format, in the FPGA module used to send each frame format : the beginning of a bit+ 8-bit data bit+ 1 bit odd parity bit+ 1 bit stop bit, baud rate for 2400. By setting the baud rate can be calculated at the frequency coefficient, the specific algorithm for the sub-frequency coefficient X = CLK/(BOUND* 2).
Platform: | Size: 1024 | Author: saibei007 | Hits:

[Com Port] uart(Verilog)

Description: RS232的verilog源代码,如果需要的可以-RS232 of Verilog source code, if necessary can be
Platform: | Size: 10240 | Author: 陈强 | Hits:

[VHDL-FPGA-Verilog] fpga_uartrw

Description: FPGA的uart控制器的verilog源程序，在cyclone II EP2C8Q208上调试运行成功-FPGA s UART controller Verilog source code, in cyclone II EP2C8Q208 debugging run successfully
Platform: | Size: 55296 | Author: 蒋斌斌 | Hits:

[VHDL-FPGA-Verilog] UART_for_FPGArar

Description: it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]-it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]
Platform: | Size: 5120 | Author: yasir ateeq | Hits:

[Industry research] UART_DESIGN

Description: The use of hardware description languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level description not only increases design productivity, but also provides unique advantages for design verification. The most dominant HDLs today are Verilog and VHDL. This application note illustrates the use of Verilog in the design and verification of a digital UART (Universal Asynchronous Receiver & Transmitter).
Platform: | Size: 141312 | Author: ltrko9kd | Hits:

[VHDL-FPGA-Verilog] UART

Description: 简易UART程序 verilog 描述-Simple UART procedure described in verilog
Platform: | Size: 18432 | Author: pan | Hits:

[Com Port] uart

Description: 串口通讯 PC发送FPGA接受后回传 verilog语言-uart verilog
Platform: | Size: 3072 | Author: 赵云 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 用FPGA开发的串口通信的程序，代码是用verilog编写的，希望对大家有用！-Serial communication with the FPGA development process, the code is written in verilog and hope for all of us!
Platform: | Size: 267264 | Author: 郭富民 | Hits:

[VHDL-FPGA-Verilog] UART

Description: the uart transmitter and receiver are used to design the data transmission for 8bit sipo and piso in verilog
Platform: | Size: 1024 | Author: prabakaran | Hits:

[VHDL-FPGA-Verilog] uart

Description: the uart model is used to design the synthies and beherival model in verilog fpga
Platform: | Size: 1024 | Author: dhanagopal | Hits:

[Other] uart_rx

Description: Tcode is in VERILOG HDL (Hardware description language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL (Hardware description language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA
Platform: | Size: 1024 | Author: hassan | Hits:

[VHDL-FPGA-Verilog] UART_IP_core_for_wishbone

Description: 基于wishbone总线的UART IP core-UART IP core based on Wishbone, generated in Verilog HDL.
Platform: | Size: 39936 | Author: 张阳 | Hits:

[Program doc] SPI-in-Verilog-implementation

Description: SPI的Verilog实现(非常的全面和详细，还带有SPI算法的注解).-SPI in Verilog implementation (a very full and detailed, but also with the SPI algorithm annotation).
Platform: | Size: 8192 | Author: 尚林 | Hits:

[VHDL-FPGA-Verilog] uart-in-verilog

Description: develop uart using verilog language-develop uart using verilog language...
Platform: | Size: 22528 | Author: Patel Dhaval P. | Hits:

[VHDL-FPGA-Verilog] UART-master

Description: FPGA Based UART in Verilog
Platform: | Size: 4096 | Author: lsyy | Hits:
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