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[VHDL-FPGA-Verilog] UART

Description: 输入时钟20M，波特率为9600，实现串口收发功能，通过修改内部分频系数可实现其它波特率的收发-Input clock 20M, the baud rate for 9600, Serial transceiver functions, by modifying the frequency of some other baud rate coefficient can realize the transceiver
Platform: | Size: 7168 | Author: 杨启勇 | Hits:

[VHDL-FPGA-Verilog] de1_t1

Description: DE1的LED流水灯，数码管显示，可修改参数完成自定义的显示，有UART串口通信代码，VGA信号显示图片。-DE1 of the LED water lamp, LED display, you can modify the parameters to complete a custom show that UART serial communication code, VGA signal display pictures.
Platform: | Size: 38280192 | Author: guowei | Hits:

[VHDL-FPGA-Verilog] UART_DMA

Description: 基于DE1的nios的串口sdram通信例程-Based on DE1' s nios serial communication routines sdram
Platform: | Size: 11353088 | Author: 李 | Hits:

[VHDL-FPGA-Verilog] audio

Description: 基于DE1开发板，实现录音和播放功能，并可将存入sram中的语言数据通过uart传回电脑。-Based on DE1 development board, recording and playback functions, and can be stored in sram language data back to the computer via uart.
Platform: | Size: 14336 | Author: zhanghui | Hits:

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