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[VHDL-FPGA-Verilog] adder4

Description: 是用verilog写得加法器以及计数器里面有测试文件（testbench），对于初学者来说这个可以用来参考下-Is written in Verilog adder and counter inside a test file (testbench), for beginners this can be used to reference the next
Platform: | Size: 1024 | Author: olive | Hits:

[Other Embeded program] systemc

Description: Systemc实现一个加法器，一个乘法器，一个十选一器，并在testbench内检测其正确性。 适用于systemc入门。-Using Systemc for the realization of a adder, a multiplier, a decimator, and within a testbench for their functionalities . Designed for Systemc or C++ beginner .
Platform: | Size: 3072 | Author: 安丽华 | Hits:

[VHDL-FPGA-Verilog] TB_VHDL(adder)

Description: 加法器的VHDL源码及其对于的仿真Testbench 文件的编写-VHDL Code about adder for the "Simple Test Bench" example VHDL Code about adder for the "Simple Test Bench" example
Platform: | Size: 1024 | Author: 帅哥新 | Hits:

[VHDL-FPGA-Verilog] counter

Description: 计数器的VHDL源码及其对于的仿真Testbench 文件的编写-VHDL Code about counter for the "Simple Test Bench" example VHDL Code about adder for the "Simple Test Bench" example
Platform: | Size: 1024 | Author: 帅哥新 | Hits:

[Software Engineering] test_bench_8bitserialadder

Description: testbench for 8 bit serial binary adder
Platform: | Size: 6144 | Author: harsha | Hits:

[Other] Full-Adder

Description: 用VHDL实现的全加器，采用dataflow style编写，是学习VHDL入门级的好范例. 包括主程序和测试程序-Full adder by using VHDL, dataflow style writing. It is a good example of VHDL especially for the entry-level leaner（Testbench included）
Platform: | Size: 1024 | Author: chenzhang | Hits:

[VHDL-FPGA-Verilog] halfadder.v.tar

Description: Verilog Code for Half Adder Circuit with testbench code-Verilog Code for Half Adder Circuit with testbench code...
Platform: | Size: 1024 | Author: Dhaval | Hits:

[VHDL-FPGA-Verilog] fulladder.tar

Description: Verilog Code for Full Adder circuit with Testbench file-Verilog Code for Full Adder circuit with Testbench file...
Platform: | Size: 1024 | Author: Dhaval | Hits:

[ELanguage] lab1

Description: half adder code for students to practice with testbench
Platform: | Size: 588800 | Author: Ammmelia | Hits:

[VHDL-FPGA-Verilog] testbench

Description: testbench for Carry look ahead adder
Platform: | Size: 1024 | Author: amirul | Hits:

[VHDL-FPGA-Verilog] CLA_20

Description: 用verilog语言编写的CLA_20文件。CLA_20是20位超前进位加法器的源代码，该代码验证后功能正确，读者可以自行编写testbench代码进行验证。-With verilog language CLA 20 files. CLA 20 is 20 lookahead adder source code after the code verification function correctly, readers can write their own testbench code for verification.
Platform: | Size: 1024 | Author: huawei | Hits:

[VHDL-FPGA-Verilog] CLA_4

Description: 用verilog语言编写的CLA_4文件。CLA_4是4位超前进位加法器的源代码，该代码验证后功能正确，读者可以自行编写testbench代码进行验证。-With verilog language CLA 4 files. CLA 4 is a four-ahead adder source code after the code verification function correctly, readers can write their own testbench code for verification.
Platform: | Size: 1024 | Author: huawei | Hits:

[VHDL-FPGA-Verilog] 16Bit-Group-Ripple-Adder

Description: Verilog Testbench for 16Bit Group Ripple Adder
Platform: | Size: 29696 | Author: Raz | Hits:

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