Description: This is 8bit multiplier VHDL code. It s consist of full adder, ripple carry adder(4bit, 8bit) multiplier 8bit, and test bench file. This is a unsigned type.-This is 8bit multiplier VHDL code. It s consist of full adder, ripple carry adder(4bit, 8bit) multiplier 8bit, and test bench file. This is a unsigned type. Platform: |
Size: 3072 |
Author:KC.Park |
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Description: 一位全加器的VHDL源码与TEST BENCH.XILINX下通过-A full adder and the VHDL source code through TEST BENCH.XILINX Platform: |
Size: 813056 |
Author:祁才君 |
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Description: FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results.
here is what I do:
1- from core generator I choose fft core and create .vhd & .vho & .xco files.
2- I add the .xco & .vhd files to my project.
3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.-FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results.
here is what I do:
1- from core generator I choose fft core and create .vhd & .vho & .xco files.
2- I add the .xco & .vhd files to my project.
3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.
Platform: |
Size: 6144 |
Author:Jayesh |
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Description: VHDL Lab 3 – Arithmetic & State Machines
In this lab we will look at arithmetic circuits that add, subtract, and multiply numbers. Each type of circuit will be implemented in two ways: first by writing VHDL code that describes the required functionality, and second by making use of predefined subcircuits from Altera’s library of parameterized modules (LPMs). The results produced for various implementations will be compared, both in terms of the circuit structure and its speed of operation. In the final part of this lab, we introduce the requirement for a Test Bench.
-VHDL Lab 3 – Arithmetic & State Machines
In this lab we will look at arithmetic circuits that add, subtract, and multiply numbers. Each type of circuit will be implemented in two ways: first by writing VHDL code that describes the required functionality, and second by making use of predefined subcircuits from Altera’s library of parameterized modules (LPMs). The results produced for various implementations will be compared, both in terms of the circuit structure and its speed of operation. In the final part of this lab, we introduce the requirement for a Test Bench.
Platform: |
Size: 1221632 |
Author:sunyan |
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Description: vhdl code for demux. this is a simple code in vhdl for demultiplexer. the test bench is also available Platform: |
Size: 11264 |
Author:nasimus |
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Description: vhdl program of jk flip flop. positive edge triggerd. the test bench is also available with the code. a simple program to start with vhdl Platform: |
Size: 11264 |
Author:nasimus |
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Description: it is a simple code in vhdl for sine wave generator. the test bench code is also provided in ths code Platform: |
Size: 21504 |
Author:nasimus |
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Description: this a simple code to generate 4-ring counter in vhdl. the test bench is also provided with ths code. a simple progrm Platform: |
Size: 11264 |
Author:nasimus |
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Description: this a vhdl code to simulate 8b/10b encoder and decoder with a test bench-this is a vhdl code to simulate 8b/10b encoder and decoder with a test bench Platform: |
Size: 135168 |
Author:zaki-sammani |
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Description: vhdl code encoder that has a rate of half (rate = 1/2) and an example of code with its test bench Platform: |
Size: 2048 |
Author:Mostafa Helal |
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Description: vhdl code of debounce for fpga . you can open it with xilinx and test it with isim or modelsim, it s a good tutorial for writing your first vhdl code and test bench . Platform: |
Size: 891904 |
Author:Milad |
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