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[VHDL-FPGA-Verilog] HardwareUDP

Description: Hardware UDP, implementation of UDP based on Altera DE2 using Verilog
Platform: | Size: 80896 | Author: Francis Wu | Hits:

[VHDL-FPGA-Verilog] DW8051_ALL

Description: 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!
Platform: | Size: 1588224 | Author: myfingerhurt | Hits:

[TCP/IP stack] TCPIP

Description: 用C实现的完整TCP/IP协议源代码,私家珍藏的宝贝-the code of TCP/IP protocol realized by C. It s very valuable.
Platform: | Size: 657408 | Author: joe | Hits:

[VHDL-FPGA-Verilog] Verilog_UDP

Description: 辛辛苦苦找到的UDP的资料，在verilog中UDP指的是用户定义的原语。比如说大家有时候会见到“primitive...table...endtable...endendprimitive”这样的代码段，在书上只能找到大概的解释。到网上查的话又老是跟TCP/IP的UDP冲突。所以特地搜集到了这个东西，希望能帮助大家解决“用户原语”相关的问题。-UDP hard to find the information in verilog in the UDP refers to the user-defined primitives. For example, we sometimes see the " primitive ... table ... endtable ... endendprimitive" This code segment can only be found in the book about interpretation. The online search, then they are always with the TCP/IP, UDP conflict. So, specifically to collect this stuff, hoping to help people solve the " user of the original language" related issues.
Platform: | Size: 125952 | Author: 龙也 | Hits:

[DSP program] IP

Description: this a programme about dsp ,it can achieve tcp/ip communication ,the programme is corect ,i wish that you can download it .-this is a programme about dsp ,it can achieve tcp/ip communication ,the programme is corect ,i wish that you can download it .
Platform: | Size: 75776 | Author: 小龙 | Hits:

[VHDL-FPGA-Verilog] pli_socket_example_pc

Description: vpi/pli socket example code-co-verification using TCP/IP socket (hardware model : verilog+ vpi as server) (software as a client)
Platform: | Size: 26624 | Author: samuel chuang | Hits:

[VHDL-FPGA-Verilog] 101259356ethernet

Description: etherent testbeanch by using verilog hdl
Platform: | Size: 1016832 | Author: weike | Hits:

[VHDL-FPGA-Verilog] System_Demons

Description: 0.最简单的SystemC程序：hello, world. 1.用SystemC实现D触发器的例子，同时也演示了如何生成VCD波形文件。 2.用SystemC实现同步FIFO的例子。这个FIFO是从同文件夹的fifo.v（verilog代码）翻译过来的。 3.如何在SystemC中实现延时（类似verilog中的#time）的例子。 4.SystemC文档《User Guide》中的例子。注意和文挡中稍有不同的是修改了packet.h文件，重载了=和<<操作符。这其实也演示了在sc_signal中如何使用用户自定义的struct。 5.构造函数带参数的例子。 6.轮转仲裁的例子。 7.使用类摸板的例子。 8.如何在模块中包含子模块。 9.SystemC的Transaction级验证示例。 10.如何trace一个数组 11.SystemC中使用测试向量文件输入的例子。 12.SystemC采用UDP/TCP通信的例子。 13.Cadence的ncsc的例子。 -0 most simple SystemC program: hello, world. A D flip-flop using SystemC example also demonstrates how to generate VCD waveform files. Synchronous FIFO example using SystemC. FIFO is from the same folder fifo.v (Verilog code) translated. Delay (similar to verilog# time). In SystemC examples. 4.SystemC document the "User Guide" in the example. Note the slightly different cultural block is modified the packet.h file, reload = << operator. In fact, this also demonstrates how to use user-defined struct in sc_signal. Constructor with parameters example. (6) examples of web arbitration. 7. The class Moban examples. 8 module contains a sub-module. 9.SystemC of Transaction-Level Verification example. 10 How to trace an array 11.SystemC use the example of the test vector file input. 12.SystemC using the example of the UDP/TCP communication. Examples of 13.Cadence the ncsc.
Platform: | Size: 532480 | Author: sdd | Hits:

[VHDL-FPGA-Verilog] w3100tcp

Description: verilog W3100A TCP程序实现-verilog w3100A TCP/IP
Platform: | Size: 6144 | Author: weishiji | Hits:

[TCP/IP stack] MAC_verilog

Description: 以太网MAC网卡的Verilog源代码，可以节省TCP/IP协议的设计开发时间。-Verilog source code for Ethernet MAC network card, you can save the TCP/IP protocol design and development time.
Platform: | Size: 125952 | Author: lxk | Hits:

[Other] UDP

Description: 用verilog实现的UDP协议，包括arp，udp，ip分段协议等，对于想用FPGA实现TCP/IP协议的人来说，应该会起到一定的帮助作用-Implemented with verilog UDP protocols, including arp, udp, ip fragmentation protocol, etc., who want to achieve TCP/IP protocol with the FPGA people, should play a helpful role
Platform: | Size: 17408 | Author: 王江 | Hits:

[hardware design] ethernet_tri_mode

Description: 以太网通信verilo实现UDP、TCP传输。-ethernet verilog，udp，tcp
Platform: | Size: 6377472 | Author: zou | Hits:

[TCP/IP stack] macwrapper

Description: this is a Verilog code for MAC Wrapper used in TCP IP suite that is used to extract MAC function TCP frame-this is a Verilog code for MAC Wrapper used in TCP IP suite that is used to extract MAC function TCP frame
Platform: | Size: 428032 | Author: vinay | Hits:

[VHDL-FPGA-Verilog] tcp_ip_core_w_dhcp_latest.tar

Description: 以太网协议 TCP/IP/DHCP协议verilog实现(Ethernet IP/TCP/DHCP verilog source code)
Platform: | Size: 152576 | Author: 翾飞FEI | Hits:

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