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[Other resource] trellis_verlog

Description: ATSC发送端部分，ATSC标准特有的TCM编码，共6个文件，包含tb文件，已通过仿真，没有问题，verilog代码-ATSC transmitter, the ATSC standard TCM unique coding, a total of six documents, tb-contained documents, had passed through simulation, no problem, verilog code
Platform: | Size: 5756 | Author: 刘超 | Hits:

[Other resource] tb

Description: 检测上升沿的verilog程序，有验证程序，可用synplify验证
Platform: | Size: 1002 | Author: ly | Hits:

[VHDL-FPGA-Verilog] trellis_verlog

Description: ATSC发送端部分，ATSC标准特有的TCM编码，共6个文件，包含tb文件，已通过仿真，没有问题，verilog代码-ATSC transmitter, the ATSC standard TCM unique coding, a total of six documents, tb-contained documents, had passed through simulation, no problem, verilog code
Platform: | Size: 5120 | Author: 刘超 | Hits:

[Other] ahb_system_generator.tar

Description: An AHB system is made of masters slaves and interconnections. A general approach to include all possible "muxed" implementation of multi layered AHB systems and arbitrated AHB ones can be thought as an acyclic graph where every source node is a master, every destination node is a slave and every internal node is an arbiter there must be one and only one arc exiting a master and one or more entering a slave (single slave verus multi-slave or arbitrated slave) an arbiter can have as many input and output connections as needed. A bridge is a special node that collapses one or more slave nodes and a master node in a new "complex" node.
Platform: | Size: 269312 | Author: 木石 | Hits:

[VHDL-FPGA-Verilog] tb

Description: 检测上升沿的verilog程序，有验证程序，可用synplify验证-Detection of rising edge of the Verilog procedures, there is the verification process can be used to verify Synplify
Platform: | Size: 1024 | Author: ly | Hits:

[VHDL-FPGA-Verilog] masterdecoder

Description: AHB总线协议 Master实现代码，对于开发AHB总线的很有帮助-AHB bus protocol to achieve Master code, very helpful for the development of AHB bus
Platform: | Size: 1024 | Author: 龙的传人 | Hits:

[source in ebook] microcoded_TB

Description: its a verilog code for microcoded tb
Platform: | Size: 1024 | Author: vijay | Hits:

[VHDL-FPGA-Verilog] slave_tb

Description: 实现对slave模块仿真的tb，利用三态始能实现。-verilog slave tb is useful
Platform: | Size: 1024 | Author: don | Hits:

[VHDL-FPGA-Verilog] VGA

Description: 基于Verilog的VGA显示程序 用于实现FPGA对于VGA显示器的控制实现图像显示，并给出相关测试的TB文件-The VGA display program based on Verilog FPGA for implementing the control of the VGA display Image display
Platform: | Size: 1024 | Author: zhengjun | Hits:

[VHDL-FPGA-Verilog] SPI

Description: SPI verilog 代码 有代码和TB 以及文件说明-SPI verilog
Platform: | Size: 16384 | Author: wuming | Hits:

[Other systems] fsm1

Description: 序列检测代码verilog 包括tb，已经验证ok-Sequence detection code verilog tb, have verified ok
Platform: | Size: 1024 | Author: kai | Hits:

[VHDL-FPGA-Verilog] Carry_Select_Adder_Verilog

Description: 进位选择加法器，verilog实现。包含3个TB。-Carry Select Adder. Verilog fulfilled. Three testbenches included.
Platform: | Size: 3072 | Author: 张昊溢 | Hits:

[VHDL-FPGA-Verilog] DDS-verilog

Description: DDS是直接数字式频率合成器（Direct Digital Synthesizer）的英文缩写，是一项关键的数字化技术。与传统的频率合成器相比，DDS具有低成本、低功耗、高分辨率和快速转换时间等优点，广泛使用在电信与电子仪器领域，是实现设备全数字化的一个关键技术。文件写了一个DDS的例程，并编写了TB文件。-DDS is a direct digital synthesizer (Direct Digital Synthesizer) of the English abbreviation, is a key digital technology. Compared with the traditional frequency synthesizer, DDS has the advantages of low cost, low power consumption, high resolution and fast conversion time. It is widely used in the field of telecommunication and electronic instrument, which is a key technology to realize the whole digitization of equipment. The file was written with a DDS routine and a TB file was written.
Platform: | Size: 2048 | Author: 林威 | Hits:

[Other] tb

Description: 用verilog语言实现FPGA控制测频(The FPGA control measurement was realized with verilog language)
Platform: | Size: 332800 | Author: kikiGYQ | Hits:

[Com Port] flash

Description: 针对华邦的flash 的驱动，没有flash行为模型 ，但包括tb文件(Winbond flash drive)
Platform: | Size: 2048 | Author: fuxi | Hits:

[VHDL-FPGA-Verilog] pwm with tb final

Description: pwm with testbench in verilog ,synthesizable
Platform: | Size: 189440 | Author: addy007 | Hits:

[VHDL-FPGA-Verilog] code_cover_on_black_level_test_project1

Description: 视频处理的黑电平校正模块的代码覆盖率测试所用的TB(The TB for the code coverage test of the video processing black level correction module)
Platform: | Size: 91136 | Author: 莫勒 | Hits:

[VHDL-FPGA-Verilog] JK_FF

Description: verilog的JK触发器描述，附带tb测试文件。(JK flip-flop description of Verilog)
Platform: | Size: 5120 | Author: Yvonnezoey | Hits:

[VHDL-FPGA-Verilog] Verilog_1Gb_DDR3_G_Die

Description: ddr3控制器，速率可达1Gbps，语言使用verilog，已经加入tb(ddr3 controller, can be used to ddr3 control,high speed)
Platform: | Size: 33792 | Author: aikannba | Hits:

[VHDL-FPGA-Verilog] FIFO_UVM

Description: fifo uvm this is total fifo tb with uvm including score board with total uvm_topology with test cases with rtl giving proper output(this is total fifo tb with uvm including score board with total uvm_topology with test cases with rtl giving proper output)
Platform: | Size: 231424 | Author: gana123 | Hits:
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