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[VHDL-FPGA-Verilog] systolic

Description: 脉动乘法器：一个GF(2m)域上的Digit-Serial 脉动结构（Systolic）的乘法器-Pulse Multiplier: a GF (2m) domain on the Digit-Serial pulsation structure (Systolic) the multiplier
Platform: | Size: 2560000 | Author: chenyi | Hits:

[VHDL-FPGA-Verilog] Systolic_Array

Description: Multiplier using systolic array
Platform: | Size: 101376 | Author: Ali | Hits:

[VHDL-FPGA-Verilog] behavioral

Description: This is a code for systolic multiplier,it can be modified for more lenght in data input
Platform: | Size: 365568 | Author: andres calderon | Hits:

[VHDL-FPGA-Verilog] systolic_mul_D8_M193

Description: 193位8段的GF(2m)域上的Digit-Serial 脉动结构(Systolic)的乘法器-a 193bit GF(2m) Ditital-Serial Systolic Multiplier
Platform: | Size: 63488 | Author: yefeng | Hits:

[Software Engineering] Systolic-Multiplier

Description: Systolic multiplier is used to multiply 18-bit or more bit multiplication
Platform: | Size: 335872 | Author: KPSS | Hits:

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