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[
VHDL-FPGA-Verilog
]
sync(shipintongbuxinhao)
Description:
基于QuartusII环境下以模块化的形式做成的视频复合同步信号。-QuartusII-based environment to create the form of modular composite video sync signal.
Platform:
|
Size:
406528
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Author:
邵捷
|
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Search - sync veril