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[VHDL-FPGA-Verilog] stop_watch

Description: 采用Quartus2编写的电子秒表电路 实现计时、暂停等功能-Quartus2 prepared using electronic stopwatch timer circuit, suspension and other functions
Platform: | Size: 349184 | Author: gz208 | Hits:

[VHDL-FPGA-Verilog] foundatonise

Description: WATCHVER is a top level Verilog type project of a Stop Watch. DESIGN TYPE: Foundation ISE (chip V50 BG256 -6) -WATCHVER is a top level Verilog type project of a Stop Watch. DESIGN TYPE: Foundation ISE (chip V50 BG256-6)
Platform: | Size: 123904 | Author: SEEDSTART | Hits:

[VHDL-FPGA-Verilog] FPGA_A.Thien

Description: stop – watch (verilog)
Platform: | Size: 24428544 | Author: viet | Hits:

[Game Program] stop-watch

Description: stopwatch with verilog it counts up and reset
Platform: | Size: 138240 | Author: haemoon | Hits:

[Software Engineering] final_lab5

Description: Verilog code for stop watch
Platform: | Size: 3401728 | Author: wenyuan | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: 基于Verilog的秒表设计，可以在modelsim与开发板环境中正常运行。-A stop watch program based on verilog
Platform: | Size: 10425344 | Author: HYT | Hits:

[VHDL-FPGA-Verilog] clock

Description: Clock generator code in Verilog for Stop Watch
Platform: | Size: 1024 | Author: Uzair | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: Stop watch code in verilog
Platform: | Size: 3072 | Author: Uzair | Hits:

[VHDL-FPGA-Verilog] verilog-stopwatch-master

Description: verilog stop watch code for end user
Platform: | Size: 10240 | Author: nira | Hits:

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