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Description: 设计ip协议的vhdl实现，对作通讯硬件的朋友因该有所帮助-design ip agreement vhdl realization of communications hardware for a friend because of the help
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Size: 82467 |
Author: linanxin |
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Description: 设计ip协议的vhdl实现，对作通讯硬件的朋友因该有所帮助-design ip agreement vhdl realization of communications hardware for a friend because of the help
Platform: |
Size: 81920 |
Author: linanxin |
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Description: VHDL IP Stack: This IP stack for an FPGA is a complex design because of the number of layers and the complexity of each that is required. It is limited to 10Mb/s operation and is designed for a full duplex switched network. It implements the lower layers of a standard TCP/IP stack. Further implementation is needed to make it work specifically for a certain purpose (eg a web server). There is support to read and write to RAM from the PC via the parallel port as well, for debugging and tests purposes (this maybe easily removed). Note the design only supports IP and ARP frames, other protocols such as RARP and 802.2 frames are not supported.-VHDL IP Stack: This IP stack for an FPGA is a complex design because of the number of layers and the complexity of each that is required. It is limited to 10Mb/s operation and is designed for a full duplex switched network. It implements the lower layers of a standard TCP/IP stack. Further implementation is needed to make it work specifically for a certain purpose (eg a web server). There is support to read and write to RAM from the PC via the parallel port as well, for debugging and tests purposes (this maybe easily removed). Note the design only supports IP and ARP frames, other protocols such as RARP and 802.2 frames are not supported.
Platform: |
Size: 81920 |
Author: James |
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