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[Other resource] PLD与8051接口的参考设计 Xilinx提供_vhdl

Description: PLD与8051接口的参考设计 Xilinx提供的verilog源代码-PLD 8051 interface with the Xilinx Reference Design for the Verilog source code
Platform: | Size: 60288 | Author: 陈旭 | Hits:

[Other resource] 曼彻斯特编解码 Xilinx提供_vhdl

Description: 曼彻斯特编解码 Xilinx提供的VHDL的源代码-Manchester codec Xilinx provide VHDL source code
Platform: | Size: 10605 | Author: 陈旭 | Hits:

[Other resource] Xilinx-modelsim-library

Description: Xilinx的modelsim　仿真库！里面有许多库函数，对于ｖｌｏｇ或ｖｈｄｌ编程有很多好的源代码可以剪切！-Xilinx modelsim simulation library! There are many libraries, vlog or VHDL programming a lot of good source code can shear!
Platform: | Size: 32190807 | Author: 杨俊涛 | Hits:

[VHDL-FPGA-Verilog] PLD与8051接口的参考设计 Xilinx提供_vhdl

Description: PLD与8051接口的参考设计 Xilinx提供的verilog源代码-PLD 8051 interface with the Xilinx Reference Design for the Verilog source code
Platform: | Size: 60416 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] ZBT SRAM控制器参考设计vhdl_xilinx

Description: ZBT SRAM控制器参考设计，xilinx提供的VHDL源代码-ZBT SRAM controller reference design for Xilinx VHDL source code
Platform: | Size: 9216 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] 曼彻斯特编解码 Xilinx提供_vhdl

Description: 曼彻斯特编解码 Xilinx提供的VHDL的源代码-Manchester codec Xilinx provide VHDL source code
Platform: | Size: 10240 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] USB接口控制器参考设计_xilinx提供_vhdl

Description: USB接口控制器参考设计，xilinx提供的VHDL源代码-USB interface controller reference design for Xilinx VHDL source code
Platform: | Size: 460800 | Author: 陈旭 | Hits:

[Embeded-SCM Develop] Xilinx_2

Description: Xilinx Ise 官方源代码盘 第四章-Xilinx Ise official source code-Chapter IV
Platform: | Size: 1015808 | Author: guorui | Hits:

[Other Databases] Xilinx-modelsim-library

Description: Xilinx的modelsim　仿真库！里面有许多库函数，对于ｖｌｏｇ或ｖｈｄｌ编程有很多好的源代码可以剪切！-Xilinx modelsim simulation library! There are many libraries, vlog or VHDL programming a lot of good source code can shear!
Platform: | Size: 32190464 | Author: 杨俊涛 | Hits:

[Other Embeded program] Xilinx_FPGA_DESIGN&CODE

Description: 完整的FPGA连接图和调试源码，图是DSN格式，但可以直接拖进PROTEL里打开。-integrity of the connection of FPGA and debug source code, the map is DSN format, it can directly dragged into PROTEL Lane open.
Platform: | Size: 241664 | Author: | Hits:

[VHDL-FPGA-Verilog] USBXilinx

Description: 实现了串行通信接口的全部功能，符合RS-232-C标准的完整UART模块源代码，中文注解，清晰易懂，经过严格仿真测试，绝对好用。-a serial communication interface of all functions, with RS-232-C standard UART modules complete source code, Chinese notes, lucid, after a rigorous simulation tests, absolutely useful.
Platform: | Size: 462848 | Author: 张海 | Hits:

[VHDL-FPGA-Verilog] Frequence_Generator

Description: xilinx提供的频率发生器的VHDL源码，可以运行在spartan3的学习开发板上。-xilinx the frequency generator VHDL source code, spartan3 can run in the learning development board.
Platform: | Size: 849920 | Author: zhangjian | Hits:

[VHDL-FPGA-Verilog] ise

Description: FPGA/CPLD设计工具---Xilinx ISE使用详解光盘源代码，Xilinx公司推荐的FPGA/CPLD培训教材-FPGA/CPLD design tools-Xilinx ISE explain the use of CD-ROM source code, Xilinx Inc. recommended FPGA/CPLD training materials
Platform: | Size: 22214656 | Author: 文成 | Hits:

[VHDL-FPGA-Verilog] LC3-code.tar

Description: 美国计算机界泰斗级作者Yale N. Patt的LC3 CPU VHDL源码,配合《计算机系统概论》一书学习效果更佳！-The United States computer industry Author greatest level Yale N. Patt of LC3 CPU VHDL source code, with
Platform: | Size: 11264 | Author: guo | Hits:

[VHDL-FPGA-Verilog] oc_mkjpeg

Description: Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.-Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.
Platform: | Size: 3267584 | Author: Andy | Hits:

[VHDL-FPGA-Verilog] guard_against_theft

Description: 利用XC9572－PQ44（Xilinx CPLD）制作的一款家用防盗报警器的Verilog源代码及原理图，当房门打开后，15秒内若没有按下Key1,则会自动拨打设定手机号（当然，要另连接一台手机）-Using XC9572-PQ44 (Xilinx CPLD) produced by a home burglar alarm of the Verilog source code and the schematic diagram, when the door opened, within 15 seconds if there is no pressing Key1, will be set automatically dial the phone number (of course, Another connection to a mobile phone)
Platform: | Size: 918528 | Author: 李德明 | Hits:

[Other Embeded program] XPS_EMC

Description: Xilinx EDK中SOC使用外部存储器接口（EMC）的方法，并用ISP1581举例说明了如何与时分复用总线（8051单片机总线）设备进行连接，有Verilog源代码。-Xilinx EDK in SOC using external memory interface (EMC) methods, and examples of how ISP1581 with the TDM bus (8051 bus) devices to connect, there Verilog source code.
Platform: | Size: 59392 | Author: YongZhiLi | Hits:

[VHDL-FPGA-Verilog] RAM

Description: 用VHDL编写一个字长16位，容量128B的RAM控制实现程序，并进行设计综合和功能模拟 。含源程序，及实验要求。适合初学者学习使用。-VHDL prepared with a 16-bit word length, 128B of the RAM capacity to achieve process control and design of analog integrated and functional. Containing source code, and experimental requirements. Suitable for beginners learning to use.
Platform: | Size: 9216 | Author: 赵剑平 | Hits:

[Other] add4bit

Description: 一位全加器的VHDL源码与TEST BENCH.XILINX下通过-A full adder and the VHDL source code through TEST BENCH.XILINX
Platform: | Size: 813056 | Author: 祁才君 | Hits:

[Crack Hack] topic

Description: DES加密算法的VHDL和VERILOG源程序- Xilinx开源共享61EDA代码工厂-DES encryption algorithm of VHDL and VERILOG source code- Xilinx factory open source code sharing 61EDA
Platform: | Size: 274432 | Author: renkaiqiang | Hits:
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