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Description: adc verilog
用verilog编写的sigma-delta adc例子
应用在计量类adc产品
Platform: |
Size: 3174 |
Author: 张鸿 |
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Description: 运用FPGA控制AD9957的操作,调试过,运用VERILOG HDL编写-Use FPGA to control the operation of AD9957, debugging, and use the preparation of VERILOG HDL
Platform: |
Size: 904192 |
Author: px99 |
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Description: 用fpga实现的DA转换器,有说明和源码,VDHL文件。
A PLD Based Delta-Sigma DAC
Delta-Sigma modulation is the simple, yet powerful,
technique responsible for the extraordinary
performance and low cost of today s audio CD
players. The simplest Delta-Sigma DAC consists of a
Delta-Sigma modulator and a one bit DAC. Since,
both of these components can be realized using
digital circuits, it is possible to implement a low
precision Delta-Sigma DAC using a PLD.-Using FPGA to achieve the DA converter, has descriptions and source code, VDHL document. A PLD Based Delta-Sigma DACDelta-Sigma modulation is the simple, yet powerful, technique responsible for the extraordinaryperformance and low cost of today s audio CDplayers. The simplest Delta-Sigma DAC consists of aDelta-Sigma modulator and a one bit DAC. Since , both of these components can be realized usingdigital circuits, it is possible to implement a lowprecision Delta-Sigma DAC using a PLD.
Platform: |
Size: 58368 |
Author: 开心 |
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Description: adc verilog
用verilog编写的sigma-delta adc例子
应用在计量类adc产品-adc verilog Verilog prepared using sigma-delta adc examples used in the measurement adc Product category
Platform: |
Size: 3072 |
Author: 张鸿 |
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Description: 用verilog编写的sigma-deltaADC的源程序。-code of verilog for sigma delta ADC
Platform: |
Size: 4096 |
Author: 刘晓志 |
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Description: sigma delta verilog code and testbench for you to do simulation
Platform: |
Size: 1024 |
Author: zhhy3818 |
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Description: dsp通过SPI接口数据采集 sigma-delta ADC采集程序-dsp through the SPI interface, data acquisition sigma-delta ADC acquisition program
Platform: |
Size: 8192 |
Author: xingtian |
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Description: Verilog source code by James Patchell:
- Delta Sigma Modulator for doing Digital->Analog Conversion
- Aquad-bquad phase detector
- Uart Reciever
- Uart Transmitter
- One shot
Platform: |
Size: 7168 |
Author: happyuser |
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Description: verilog code for a 2nd order sigma delta modulator
Platform: |
Size: 1564672 |
Author: Alberto W. Jr |
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Description: 根据FPGA的∑-Δ D/A转换器的设计与实现策略,∑-Δ DAC的内部仅由2个10位的二进制加法器,1个10位的锁存器和一个D触发器组成,用FPGA实现时只需耗费极少的逻辑资源,即使用最小的FPGA也能实现。这是∑-Δ DAC实现的verilog语言-According to the FPGA Σ-Δ D/A converter design and implementation strategies, Σ-Δ DAC' s internal only by the two 10-bit binary adder, a 10-bit latch and a D flip-flop, with the FPGA implementations consume only minimal logic resources, using the smallest FPGA can achieve. This is the Σ-Δ DAC implementation verilog language! ! !
Platform: |
Size: 1333248 |
Author: 王凌 |
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Description: 累加器实现艾哈空间哈卡哈尽快啊哈卡哈卡快捷回复哈哈哈看(Accumulator implementation)
Platform: |
Size: 4096 |
Author: 西伯利亚牛
|
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Description: 基础的几个verilog代码实现,讲到case和task的使用。(basic verilog,use case and task ,very usual, i want some help to achieve the design of delta and sigma fractional_n divider.)
Platform: |
Size: 88064 |
Author: sana00 |
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